Abstract: An apparatus presents a clock signal in response to receiving a drive signal. The clock signal has a clock amplitude established independent of the drive signal. The apparatus includes: (a) A drive section coupled for receiving the drive signal. The drive section presents the clock signal at a clock locus in response to the drive signal. (b) An operating signal source coupled with the drive section. The operating signal source provides a supply signal to the drive section. The drive section employs the supply signal to establish the clock amplitude.

Abstract: An RF receiver front end includes a variable gain low noise amplifier and/or a variable gain mixer to provide gain variability in the receiver. This gain variability may be used during, for example, automatic gain control operations. In at least one embodiment, the variable gain LNA is a broadband device that is capable of supporting multiple wireless standards.

Abstract: An apparatus reducing non-linearity in an output signal presented at an output locus of an amplifier device having an output unit coupled with the output locus, the output unit having at least one first operating characteristic contributing to the non-linearity, includes a compensating unit coupled with the output locus. The compensating unit has at least one second operating characteristic cooperating with the at least one first operating characteristic to effect the reducing.

Abstract: A circuit and method for protecting the minimum run length in RLL code is disclosed. The circuit comprises three state processors, each having a plurality of registers, including a decision bit, an invalid bit, metric bits and path bit array, and changing state at the zero crossing point (Turning) of an RF signal, before the zero crossing point (Before) and after the zero crossing point (After). A metric computing unit is used to calculate the metrics at the points of turning, before and after corresponding to the EFM (Eight-Fourteen Modulation) signal. A timing unit is used to generate control signals to the state processors and metric computing unit according to the EFM signal. Then the protecting circuit comprises a computing unit to control the decision bit, the invalid bit, the metric bits and path bit array and generates correct output signals according to the control signals and the metrics.

Abstract: A circuit and method for protecting the minimum run length in RLL code is disclosed. The circuit comprises three state processors, each having a plurality of registers, including a decision bit, an invalid bit, metric bits and path bit array, and changing state at the zero crossing point (Turning) of an RF signal, before the zero crossing point (Before) and after the zero crossing point (After). A metric computing unit is used to calculate the metrics at the points of turning, before and after corresponding to the EFM (Eight-Fourteen Modulation) signal. A timing unit is used to generate control signals to the state processors and metric computing unit according to the EFM signal. Then the protecting circuit comprises a computing unit to control the decision bit, the invalid bit, the metric bits and path bit array and generates correct output signals according to the control signals and the metrics.