Patents by Inventor Jinghua Zhu

Jinghua Zhu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240106360
    Abstract: The present disclosure provides a method for reducing the electromagnetic vibration of a fractional slot concentrated winding (FSCW) permanent magnet (PM) motor, which provides a guidance for the low vibration design of FSCW PM motor. The implementation of the method includes: Based on Nyquist Shannon sampling theorem, the modulation effect of electromagnetic force in the air gap is obtained, and the electromagnetic force component that contributes the most to the electromagnetic vibration of the FSCW PM motor is determined. The equivalent analytical model of PM flux density is established to obtain the phase relationship between different flux density harmonics. According to Maxwell stress equation, the internal relationship between each order of flux density harmonics and electromagnetic force harmonics is obtained. A new magnet structure of the PM motor is designed, and specific flux density harmonics are injected to reduce the electromagnetic force and electromagnetic vibration of the FSCW PM motor.
    Type: Application
    Filed: March 2, 2021
    Publication date: March 28, 2024
    Applicant: Jiangsu University
    Inventors: Wenxiang ZHAO, Shengdao ZHU, Guohai LIU, Jinghua JI
  • Patent number: 11912729
    Abstract: Provided are a boron-silicon heterocyclic compound having a structure represented by formula 1, a display device and a display apparatus. In formula 1, L1 and L2 are each a single bond, C6-C30 arylene, C6-C30 fused arylene, C4-C30 heteroarylene, or C4-C30 fused heteroarylene; D1 and D2 are each a substituted or unsubstituted C6-C60 aryl, a substituted or unsubstituted C4-C60 heteroaryl, a substituted or unsubstituted C10-C60 fused aryl, a substituted or unsubstituted C8-C30 fused heteroaryl, or a substituted or unsubstituted diphenylamino. The compound has a strong inductive effect and can reduce the driving voltage of the device. The silacyclopentadiene having a silicon atom as spiro-atom can effectively improve the solubility of the material, which is beneficial to the cleaning of the vapor deposition mask. In addition, the compound has a higher triplet energy level to effectively transfer energy to the luminous body, and improves the efficiency of the device.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: February 27, 2024
    Assignees: WUHAN TIANMA MICRO-ELECTRONICS CO., LTD., WUHAN TIANMA MICROELECTRONICS CO., LTD. SHANGHAI BRANCH
    Inventors: Lei Zhang, Wei Gao, Jinghua Niu, Ying Liu, Dongyang Deng, Yan Lu, Hongyan Zhu, Xia Li
  • Patent number: 11688704
    Abstract: An integrated circuit package and a system including the integrated circuit package as well as a process for assembling the integrated circuit package are provided to improve integrated circuit power delivery. The integrated circuit package includes a first die having a plurality of pads formed in the first die and exposed on a top surface of the first die, at least one post on the first die, and a substrate including one or more redistribution layers. Each post in the at least one post spans at least two pads on the first die utilized for power distribution, and the first die is connected to the substrate via the at least one post.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: June 27, 2023
    Assignee: Futurewei Technologies, Inc.
    Inventors: Shiqun Gu, Jinghua Zhu, Hongying Zhang, Jun Xia, Wangsheng Xie, Shuangfu Wang, Hong Liu, Liming Zhao, Hongquan Sun
  • Publication number: 20220148988
    Abstract: An integrated circuit package and a system including the integrated circuit package as well as a process for assembling the integrated circuit package are provided to improve integrated circuit power delivery. The integrated circuit package includes a first die having a plurality of pads formed in the first die and exposed on a top surface of the first die, at least one post on the first die, and a substrate including one or more redistribution layers. Each post in the at least one post spans at least two pads on the first die utilized for power distribution, and the first die is connected to the substrate via the at least one post.
    Type: Application
    Filed: January 21, 2022
    Publication date: May 12, 2022
    Applicant: Futurewei Technologies, Inc.
    Inventors: Shiqun Gu, Jinghua Zhu, Hongying Zhang, Jun Xia, Wangsheng Xie, Shuangfu Wang, Hong Liu, Liming Zhao, Hongquan Sun
  • Patent number: 11233025
    Abstract: An integrated circuit package and a system including the integrated circuit package as well as a process for assembling the integrated circuit package are provided to improve integrated circuit power delivery. The integrated circuit package includes a first die having a plurality of pads formed in the first die and exposed on a top surface of the first die, at least one post on the first die, and a substrate including one or more redistribution layers. Each post in the at least one post spans at least two pads on the first die utilized for power distribution, and the first die is connected to the substrate via the at least one post.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: January 25, 2022
    Assignee: Futurewei Technologies, Inc.
    Inventors: Shiqun Gu, Jinghua Zhu, Hongying Zhang, Jun Xia, Wangsheng Xie, Shuangfu Wang, Hong Liu, Liming Zhao, Hongquan Sun
  • Patent number: 10658335
    Abstract: An integrated circuit package and a system including the integrated circuit package as well as a process for assembling the integrated circuit package are provided. The integrated circuit package includes a first die manufactured on a first wafer utilizing a first node size, a second die manufactured on a second wafer utilizing a second node size, and a substrate coupled to the second die at a plurality of bump sites on a bottom surface of the second die. The first die may be mounted on a top surface of the second die utilizing a hybrid wafer bonding technique, micro bumps, or electrode-less plating.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: May 19, 2020
    Assignee: Futurewei Technologies, Inc.
    Inventors: Shiqun Gu, Yu Lin, Jinghua Zhu, Guofang Jiao
  • Publication number: 20180366442
    Abstract: An integrated circuit package and a system including the integrated circuit package as well as a process for assembling the integrated circuit package are provided. The integrated circuit package includes a first die manufactured on a first wafer utilizing a first node size, a second die manufactured on a second wafer utilizing a second node size, and a substrate coupled to the second die at a plurality of bump sites on a bottom surface of the second die. The first die may be mounted on a top surface of the second die utilizing a hybrid wafer bonding technique, micro bumps, or electrode-less plating.
    Type: Application
    Filed: January 25, 2018
    Publication date: December 20, 2018
    Inventors: Shiqun Gu, Yu Lin, Jinghua Zhu, Guofang Jiao
  • Publication number: 20180350762
    Abstract: An integrated circuit package and a system including the integrated circuit package as well as a process for assembling the integrated circuit package are provided to improve integrated circuit power delivery. The integrated circuit package includes a first die having a plurality of pads formed in the first die and exposed on a top surface of the first die, at least one post on the first die, and a substrate including one or more redistribution layers. Each post in the at least one post spans at least two pads on the first die utilized for power distribution, and the first die is connected to the substrate via the at least one post.
    Type: Application
    Filed: January 25, 2018
    Publication date: December 6, 2018
    Inventors: Shiqun Gu, Jinghua Zhu, Hongying Zhang, Jun Xia, Wangsheng Xie, Shuangfu Wang, Hong Liu, Liming Zhao, Hongquan Sun
  • Patent number: 7289418
    Abstract: An optical disk with an erasable surface of the present invention includes a transparent substrate, a recording layer, and a reflective layer, and an erasable writing layer. The recording layer is formed between the transparent substrate and the reflective layer, and the reflective layer is formed between the recording layer and the erasable writing layer. The optical disk may further include a protective layer, and the protective layer is formed between the erasable writing layer and the reflective layer. The invention also discloses a method of manufacturing such optical disk.
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: October 30, 2007
    Inventor: Jinghua Zhu
  • Publication number: 20050094544
    Abstract: An optical disk with an erasable surface of the present invention includes a transparent substrate, a recording layer, and a reflective layer, and an erasable writing layer. The recording layer is formed between the transparent substrate and the reflective layer, and the reflective layer is formed between the recording layer and the erasable writing layer. The optical disk may further include a protective layer, and the protective layer is formed between the erasable writing layer and the reflective layer. The invention also discloses a method of manufacturing such optical disk.
    Type: Application
    Filed: January 30, 2004
    Publication date: May 5, 2005
    Inventor: Jinghua Zhu