Patents by Inventor Jing-Hwang Yang
Jing-Hwang Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12272725Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.Type: GrantFiled: June 26, 2023Date of Patent: April 8, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jyun-Ying Lin, Hsin-Li Cheng, Jing-Hwang Yang, Felix Ying-Kit Tsui, Chien-Li Kuo
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Patent number: 12259604Abstract: A method of fabricating an optical device comprises steps of forming a silicon-based optical component in a substrate; depositing an ILD layer on the substrate and the silicon-based optical component; forming a thermal tuning assembly comprising a first metallic material in the ILD layer and above the silicon-based optical component, wherein the thermal tuning assembly comprises a core above the silicon-based optical component, a plurality of grids spaced apart from the core, and a pair of neck portions connecting the grids to the core, wherein a width of a strip in each grid is greater than a width of the core; forming at least one conductive plug comprising the first metallic material penetrating the ILD layer and coupled to the silicon-based optical component; and forming a plurality of conductive lines comprising a second metallic material coupled to the thermal tuning assembly.Type: GrantFiled: March 28, 2023Date of Patent: March 25, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Wen-Shun Lo, Jing-Hwang Yang, Yingkit Felix Tsui
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Publication number: 20250048781Abstract: A modulator heater structure may include a plurality of regions having different thicknesses. For example, a heater ring of the modulator heater structure may have a first thickness. A heater pad of the modulator heater structure, that is configured to provide an electrical current to the heater ring, may have a second thickness that is greater than the first thickness. The lesser thickness of the heater ring of the modulator heater structure provides high electrical resistance in the heater ring, which enables the heater ring to quickly and efficiently generate heat. The greater thickness of the heater pad provides low electrical resistance in the second region, which enables the electrical current to be efficiently provided through the heater pad to the heater ring with reduced heat dissipation in the hear pad due to the lower electrical current dissipation in the heater pad.Type: ApplicationFiled: August 4, 2023Publication date: February 6, 2025Inventors: Wen-Shun LO, Sheng Kai YEH, Jing-Hwang YANG, Chi-Yuan SHIH, Shih-Fen HUANG, YingKit Felix TSUI
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Publication number: 20240402521Abstract: An optical modulator structure in a photonic integrated circuit includes an L-shaped P-N junction at an optical mode of the optical modulator structure (e.g., an area of the optical modulator structure in which light is generated). The L-shaped P-N junction provides increased area of overlap of the P-N junction at the optical mode relative to another type of junction, such as a horizontal junction or I-shaped junction. The increased area of overlap may enable the optical modulator structure to achieve a greater modulation efficiency.Type: ApplicationFiled: May 30, 2023Publication date: December 5, 2024Inventors: Wen-Shun LO, Ta-Wei CHOU, Chih-Tsung SHIH, Jing-Hwang YANG, Chi-Yuan SHIH, YingKit Felix TSUI, Shih-Fen HUANG
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Publication number: 20240377659Abstract: The present disclosure provides an optical modulating structure. The optical modulating structure includes a lower member extending along an insulating layer, a first protrusion over the lower member, and a second protrusion over the lower member and separated from the first protrusion. A first mask layer is formed over the optical modulating structure, wherein the first mask layer covers the second protrusion and a first portion of the lower member between the first protrusion and the second protrusion. A first doping region is formed in an exposed portion of the lower member and at least a portion of an exposed sidewall of the first protrusion. A dielectric layer is formed between the first protrusion and the second protrusion. A method for manufacturing the optical modulating structure is also provided.Type: ApplicationFiled: May 10, 2023Publication date: November 14, 2024Inventors: WEN-SHUN LO, YINGKIT FELIX TSUI, JING-HWANG YANG
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Publication number: 20240369764Abstract: A semiconductor structure includes a grating coupler structure, a circuit component separated from the grating coupler structure, an inter level dielectric layer, a capping layer over the inter level dielectric layer, and a passivation layer over the capping layer. The inter level dielectric layer has a first refractive index, the capping layer has second refractive index, and the passivation layer has a third refractive index. The second refractive index is greater than the first refractive index, and is greater than the third refractive index.Type: ApplicationFiled: July 21, 2024Publication date: November 7, 2024Inventors: CHIH-TSUNG SHIH, WEI-KANG LIU, SUI-YING HSU, JING-HWANG YANG, YINGKIT FELIX TSUI
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Publication number: 20240353617Abstract: A waveguide structure and an optical modulator structure of a photonic integrated circuit are formed in a dielectric region above a substrate of a semiconductor device. Openings are then formed through the dielectric region and to the substrate so that material can be removed from the substrate to form air gaps between the substrate and the dielectric region. The openings are then sealed by depositing dielectric material in the openings. Sealing the openings reduces the likelihood of exposure of the dielectric region and other regions of the semiconductor device to exposure to environmental elements such as humidity and oxygen. The reduced likelihood of exposure to these environmental elements, due to sealing the openings, may reduce the likelihood and/or rate of formation of defects in the dielectric region and the other regions of the semiconductor device.Type: ApplicationFiled: April 21, 2023Publication date: October 24, 2024Inventors: Wen-Shun LO, Jing-Hwang YANG, YingKit Felix TSUI
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Patent number: 12124083Abstract: A semiconductor structure includes a substrate, a grating coupler structure over the substrate, a multi-layers film structure over the grating coupler structure. The multi-layers film structure include a first layer including a first refractive index, a second layer over the first layer and including a second refractive index and a third layer over the second layer and including a third refractive index. The second refractive index is greater than the first refractive index and is greater than the third refractive index of the third layer, and a thickness of each layer of the multi-layers film structure is within a range from ?/4 to ?2, ? is a wavelength of light.Type: GrantFiled: August 3, 2022Date of Patent: October 22, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chih-Tsung Shih, Wei-Kang Liu, Sui-Ying Hsu, Jing-Hwang Yang, Yingkit Felix Tsui
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Publication number: 20240329435Abstract: A method of fabricating an optical device comprises steps of forming a silicon-based optical component in a substrate; depositing an ILD layer on the substrate and the silicon-based optical component; forming a thermal tuning assembly comprising a first metallic material in the ILD layer and above the silicon-based optical component, wherein the thermal tuning assembly comprises a core above the silicon-based optical component, a plurality of grids spaced apart from the core, and a pair of neck portions connecting the grids to the core, wherein a width of a strip in each grid is greater than a width of the core; forming at least one conductive plug comprising the first metallic material penetrating the ILD layer and coupled to the silicon-based optical component; and forming a plurality of conductive lines comprising a second metallic material coupled to the thermal tuning assembly.Type: ApplicationFiled: March 28, 2023Publication date: October 3, 2024Inventors: Wen-Shun LO, Jing-Hwang YANG, Yingkit Felix TSUI
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Publication number: 20240113091Abstract: The present disclosure provides a package with a semiconductor structure and a method for manufacturing the semiconductor structure. In some embodiments, a photonic semiconductor structure includes a substrate having a first side and a second side opposite to each other, a first redistribution layer disposed on the first side, an interconnect structure disposed on the second side of the substrate, a metal reflector disposed in the interconnect structure, a dielectric layer disposed over the interconnect structure, and a grating coupler disposed in the dielectric layer and overlapping the metal reflector.Type: ApplicationFiled: January 17, 2023Publication date: April 4, 2024Inventors: WEN-SHUN LO, JING-HWANG YANG, YINGKIT FELIX TSUI
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Publication number: 20240045141Abstract: A semiconductor structure includes a substrate, a grating coupler structure over the substrate, a multi-layers film structure over the grating coupler structure. The multi-layers film structure include a first layer including a first refractive index, a second layer over the first layer and including a second refractive index and a third layer over the second layer and including a third refractive index. The second refractive index is greater than the first refractive index and is greater than the third refractive index of the third layer, and a thickness of each layer of the multi-layers film structure is within a range from ?/4 to ?2, ? is a wavelength of light.Type: ApplicationFiled: August 3, 2022Publication date: February 8, 2024Inventors: CHIH-TSUNG SHIH, WEI-KANG LIU, SUI-YING HSU, JING-HWANG YANG, YINGKIT FELIX TSUI
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Patent number: 11828722Abstract: A biological device includes a substrate, a gate electrode, and a sensing well. The substrate includes a source region, a drain region, a channel region, a body region, and a sensing region. The channel region is disposed between the source region and the drain region. The sensing region is at least disposed between the channel region and the body region. The gate electrode is at least disposed on or above the channel region of the substrate. The sensing well is at least disposed adjacent to the sensing region.Type: GrantFiled: December 16, 2019Date of Patent: November 28, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ta-Chuan Liao, Chien-Kuo Yang, Yi-Shao Liu, Tung-Tsun Chen, Chan-Ching Lin, Jui-Cheng Huang, Felix Ying-Kit Tsui, Jing-Hwang Yang
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Publication number: 20230375499Abstract: A biological device includes a substrate, a gate electrode, and a sensing well. The substrate includes a source region, a drain region, a channel region, a body region, and a sensing region. The channel region is disposed between the source region and the drain region. The sensing region is at least disposed between the channel region and the body region. The gate electrode is at least disposed on or above the channel region of the substrate. The sensing well is at least disposed adjacent to the sensing region.Type: ApplicationFiled: July 31, 2023Publication date: November 23, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ta-Chuan LIAO, Chien-Kuo YANG, Yi-Shao LIU, Tung-Tsun CHEN, Chan-Ching LIN, Jui-Cheng HUANG, Felix Ying-Kit TSUI, Jing-Hwang YANG
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Publication number: 20230369526Abstract: A stacked (or vertically arranged) photodetector having at least one contact region on a germanium sensing region. Including the at least one contact on the germanium sensing region reduces the amount of surface area of the germanium sensing region that is interfaced with a substrate (e.g., a silicon substrate) in which the germanium sensing region is included. This reduces the amount of lattice mismatch reduces the amount of misfit defects for the germanium sensing region, which reduces the dark current for the photodetector. The reduced amount of dark current may increase the photosensitivity of the photodetector, may increase low-light performance of the photodetector, and/or may decrease noise and other defects in images and/or light captured by the photodetector, among other examples.Type: ApplicationFiled: May 12, 2022Publication date: November 16, 2023Inventors: Chen-Hao CHIANG, Chih-Ming CHEN, Jing-Hwang YANG
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Publication number: 20230361166Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.Type: ApplicationFiled: June 26, 2023Publication date: November 9, 2023Inventors: Jyun-Ying Lin, Hsin-Li Cheng, Jing-Hwang Yang, Felix Ying-Kit Tsui, Chien-Li Kuo
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Patent number: 11688762Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.Type: GrantFiled: November 25, 2020Date of Patent: June 27, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jyun-Ying Lin, Hsin-Li Cheng, Jing-Hwang Yang, Felix Ying-Kit Tsui, Chien-Li Kuo
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Patent number: 11508658Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a semiconductor substrate having a first surface and a first optical coupler disposed on the first surface of the semiconductor substrate. The first optical coupler includes a first surface facing away from the first surface of the semiconductor substrate and a first lateral surface connected to the first surface of the first optical coupler. The first surface of the first optical coupler and the first lateral surface of the optical coupler define an angle greater than 90 degrees. A method of manufacturing a semiconductor device package is also disclosed.Type: GrantFiled: April 1, 2020Date of Patent: November 22, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hau-Yan Lu, Felix Ying-Kit Tsui, Jing-Hwang Yang, Feng Yuan
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Publication number: 20210313259Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a semiconductor substrate having a first surface and a first optical coupler disposed on the first surface of the semiconductor substrate. The first optical coupler includes a first surface facing away from the first surface of the semiconductor substrate and a first lateral surface connected to the first surface of the first optical coupler. The first surface of the first optical coupler and the first lateral surface of the optical coupler define an angle greater than 90 degrees. A method of manufacturing a semiconductor device package is also disclosed.Type: ApplicationFiled: April 1, 2020Publication date: October 7, 2021Inventors: HAU-YAN LU, FELIX YING-KIT TSUI, JING-HWANG YANG, FENG YUAN
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Publication number: 20210104598Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.Type: ApplicationFiled: November 25, 2020Publication date: April 8, 2021Inventors: Jyun-Ying Lin, Hsin-Li Cheng, Jing-Hwang Yang, Felix Ying-Kit Tsui, Chien-Li Kuo
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Patent number: 10868110Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.Type: GrantFiled: April 18, 2019Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jyun-Ying Lin, Hsin-Li Cheng, Jing-Hwang Yang, Felix Ying-Kit Tsui, Chien-Li Kuo