Patents by Inventor Jing Jia
Jing Jia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20200126633Abstract: A method for controlling the quality of traditional Chinese patent medicines is based on metagenomics. The method includes extracting genomic DNA of a sample of the traditional Chinese patent medicine, constructing a library of the genomic DNA based on a high-throughput sequencing platform, and performing metagenomic sequencing. The data obtained from the metagenomic sequencing is processed to obtain the ITS2 sequence of the traditional Chinese patent medicine sample A BLAST alignment is performed on the ITS2 sequence in the DNA Barcoding System for Identifying Herbal Medicine, to obtain species identification results. The obtained identification results are compared with the labeled species of the traditional Chinese patent medicine to obtain a conclusion about the quality of the traditional Chinese patent medicine sample.Type: ApplicationFiled: June 28, 2017Publication date: April 23, 2020Inventors: Jingyuan SONG, Tianyi XIN, Zhichao XU, Jing JIA
-
Patent number: 10365829Abstract: A memory transaction-level modeling method and a memory transaction-level modeling system are provided. The memory transaction-level modeling method is used for simulating the operation of outputting at least one command to the memory. The memory includes a plurality of banks each of which corresponds with a bank status table. The memory transaction-level modeling method includes the following steps: An event is received. Whether one of the bank status tables is needed to be updated is determined. If one of the bank status tables is needed to be updated, this bank status table is recovered according to a TMP queue. A command is outputted to the memory according to a command queue. The outputted command is stored in the TMP queue. Some of the bank status tables are updated and others of the bank status tables are kept unchanged.Type: GrantFiled: December 27, 2016Date of Patent: July 30, 2019Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yao-Hua Chen, Che-Wei Hsu, Juin-Ming Lu, Wei-Shiang Lin, Jing-Jia Liou, Chih-Tsun Huang
-
Publication number: 20190151272Abstract: The present invention relates to a composition comprising a lithium salt of an N-substituted glycine compound and a carrier, wherein the lithium salt of the N-substituted glycine compound is of Formula (I): in which R1, R2, and R3 each are independently hydrogen, alkyl, alkenyl, alkynyl, aralkyl, carbocyclyl, aryl, or heteroaryl, or one of R1, R2, and R3 is absent. Also provided in the present invention is a method of mitigating at least one symptom of a neuropsychiatric disorder, comprising administering to a subject in need thereof the lithium salt of an N-substituted glycine compound of Formula (I).Type: ApplicationFiled: January 18, 2019Publication date: May 23, 2019Applicant: SyneuRx International (Taiwan) Corp.Inventors: Guochuan Emil Tsai, Ching-Hsun Huang, Han-Yi Hsieh, Jing-Jia Huang, Ching-Cheng Wang
-
Patent number: 10226442Abstract: The present invention relates to a composition comprising a lithium salt of an N-substituted glycine compound and a carrier, wherein the lithium salt of the N-substituted glycine compound is of Formula (I): in which R1, R2, and R3 each are independently hydrogen, alkyl, alkenyl, alkynyl, aralkyl, carbocyclyl, aryl, or heteroaryl, or one of R1, R2, and R3 is absent. Also provided in the present invention is a method of mitigating at least one symptom of a neuropsychiatric disorder, comprising administering to a subject in need thereof the lithium salt of an N-substituted glycine compound of Formula (I).Type: GrantFiled: July 10, 2017Date of Patent: March 12, 2019Assignee: SyneuRx International (Taiwan) Corp.Inventors: Guochuan Emil Tsai, Ching-Hsun Huang, Han-Yi Hsieh, Jing-Jia Huang, Ching-Cheng Wang
-
Patent number: 10199523Abstract: A surface region of a semiconductor material on a surface of a semiconductor device is doped during its manufacture, by coating the surface region of the semiconductor material with a dielectric material surface layer and locally heating the surface of the semiconductor material in an area to be doped to locally melt the semiconductor material with the melting being performed in the presence of a dopant source. The heating is performed in a controlled manner such that a region of the surface of the semiconductor material in the area to be doped is maintained in a molten state without refreezing for a period of time greater than one microsecond and the dopant from the dopant source is absorbed into the molten semiconductor. The semiconductor device includes a semiconductor material structure in which a junction is formed and may incorporate a multi-layer anti-reflection coating.Type: GrantFiled: June 25, 2015Date of Patent: February 5, 2019Assignees: NEWSOUTH INNOVATIONS PTY LIMITED, SUNTECH POWER INTERNATIONAL LTD.Inventors: Alison Maree Wenham, Ziv Hameiri, Jing Jia Ji, Ly Mai, Zhengrong Shi, Budi Tjahjono, Stuart Ross Wenham
-
Publication number: 20190008813Abstract: The present invention relates to a composition comprising a lithium salt of an N-substituted glycine compound and a carrier, wherein the lithium salt of the N-substituted glycine compound is of Formula (I): in which R1, R2, and R3 each are independently hydrogen, alkyl, alkenyl, alkynyl, aralkyl, carbocyclyl, aryl, or heteroaryl, or one of R1, R2, and R3 is absent. Also provided in the present invention is a method of mitigating at least one symptom of a neuropsychiatric disorder, comprising administering to a subject in need thereof the lithium salt of an N-substituted glycine compound of Formula (I).Type: ApplicationFiled: July 10, 2017Publication date: January 10, 2019Inventors: Guochuan Emil Tsai, Ching-Hsun Huang, Han-Yi Hsieh, Jing-Jia Huang, Ching-Cheng Wang
-
Publication number: 20180318243Abstract: Methods for treating central nervous system (CNS) disorders or attenuating pain with a lithium benzoate compound.Type: ApplicationFiled: July 19, 2018Publication date: November 8, 2018Applicant: SyneuRx International (Taiwan) Corp.Inventors: Guochuan Emil Tsai, Hong-Jung Chen, Wei-En Hsu, Weiju Chang, Jing-Jia Huang
-
Publication number: 20180074702Abstract: A memory transaction-level modeling method and a memory transaction-level modeling system are provided. The memory transaction-level modeling method is used for simulating the operation of outputting at least one command to the memory. The memory includes a plurality of banks each of which corresponds with a bank status table. The memory transaction-level modeling method includes the following steps: An event is received. Whether one of the bank status tables is needed to be updated is determined. If one of the bank status tables is needed to be updated, this bank status table is recovered according to a TMP queue. A command is outputted to the memory according to a command queue. The outputted command is stored in the TMP queue. Some of the bank status tables are updated and others of the bank status tables are kept unchanged.Type: ApplicationFiled: December 27, 2016Publication date: March 15, 2018Inventors: Yao-Hua Chen, Che-Wei Hsu, Juin-Ming Lu, Wei-Shiang Lin, Jing-Jia Liou, Chih-Tsun Huang
-
Patent number: 9842180Abstract: A NoC timing power estimating method includes: estimating a plurality of transmission timing of a plurality of transmission units of at least a packet, the transmission timing indicating respective time points at which the transmission units enter/leave a plurality of passing elements of the NoC; based on the transmission timing of the transmission units, estimating respective circuit states and respective power states of the passing elements of the NoC, the circuit state indicating an operation state of the passing element and the power state being related to the circuit state; and based on the power states of the passing elements of the NoC, estimating power consumption of the NoC.Type: GrantFiled: December 30, 2014Date of Patent: December 12, 2017Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Ting-Shuo Hsu, Jing-Jia Liou, Jih-Sheng Shen, Juin-Ming Lu
-
Publication number: 20170169150Abstract: A method for system simulation includes the steps of: simulating the operation of a first circuit during N clock periods based on a first model and a simulation granularity, and adjusting the simulation granularity based on the input signal or the output signal corresponding to the first model. A non-transitory computer-readable recording medium corresponding to the method is also provided.Type: ApplicationFiled: December 29, 2015Publication date: June 15, 2017Inventors: YAO-HUA CHEN, CHE-WEI HSU, JUIN-MING LU, TING-SHUO HSU, JING-JIA LIOU, CHIH-TSUN HUANG
-
Patent number: 9385247Abstract: A method of forming an oxide layer on an exposed surface of a semiconductor device which contains a p-n junction is disclosed, the method comprising: immersing the exposed surface of the semiconductor device in an electrolyte; producing an electric field in the semiconductor device such that the p-n junction is forward-biased and the exposed surface is anodic; and electrochemically oxidizing the exposed surface to form an oxide layer.Type: GrantFiled: May 23, 2014Date of Patent: July 5, 2016Assignee: NEWSOUTH INNOVATIONS PTY LIMITEDInventors: Valantis Vais, Alison Joan Lennon, Stuart Ross Wenham, Jing Jia Ji, Alison Maree Wenham, Jingnan Tong, Xi Wang
-
Publication number: 20160149780Abstract: A NoC timing power estimating method includes: estimating a plurality of transmission timing of a plurality of transmission units of at least a packet, the transmission timing indicating respective time points at which the transmission units enter/leave a plurality of passing elements of the NoC; based on the transmission timing of the transmission units, estimating respective circuit states and respective power states of the passing elements of the NoC, the circuit state indicating an operation state of the passing element and the power state being related to the circuit state; and based on the power states of the passing elements of the NoC, estimating power consumption of the NoC.Type: ApplicationFiled: December 30, 2014Publication date: May 26, 2016Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Ting-Shuo HSU, Jing-Jia LIOU, Jih-Sheng SHEN, Juin-Ming LU
-
Patent number: 9269851Abstract: A method of depositing metal on an exposed surface of a p-type semiconductor region of a semiconductor device comprising a p-n junction is disclosed, the method comprising: immersing the exposed surface of the p-type semiconductor region on which the metal is to be deposited in a solution of metal ions; producing an electric field in the semiconductor device such that the p-n junction is forward biased; electrochemically depositing the metal on the exposed surface of the p-type semiconductor region of the semiconductor device by reduction of metal ions in the solution.Type: GrantFiled: November 12, 2012Date of Patent: February 23, 2016Assignee: NEWSOUTH INNOVATIONS PTY LIMITEDInventors: Valantis Vais, Alison Joan Lennon, Stuart Ross Wenham, Jing Jia Ji, Alison Maree Wenham
-
Publication number: 20150318413Abstract: A surface region of a semiconductor material on a surface of a semiconductor device is doped during its manufacture, by coating the surface region of the semiconductor material with a dielectric material surface layer and locally heating the surface of the semiconductor material in an area to be doped to locally melt the semiconductor material with the melting being performed in the presence of a dopant source. The heating is performed in a controlled manner such that a region of the surface of the semiconductor material in the area to be doped is maintained in a molten state without refreezing for a period of time greater than one microsecond and the dopant from the dopant source is absorbed into the molten semiconductor. The semiconductor device includes a semiconductor material structure in which a junction is formed and may incorporate a multi-layer anti-reflection coating.Type: ApplicationFiled: June 25, 2015Publication date: November 5, 2015Applicants: Suntech Power International Ltd., NewSouth Innovations Pty LimitedInventors: Alison Maree Wenham, Ziv Hameiri, Ji Jing Jia, Ly Mai, Shi Zhengrong, Budi Tjahjono, Stuart Ross Wenham
-
Patent number: 9136126Abstract: A surface region of a semiconductor material on a surface of a semiconductor device is doped during its manufacture, by coating the surface region of the semiconductor material with a dielectric material surface layer and locally heating the surface of the semiconductor material in an area to be doped to locally melt the semiconductor material with the melting being performed in the presence of a dopant source. The heating is performed in a controlled manner such that a region of the surface of the semiconductor material in the area to be doped is maintained in a molten state without refreezing for a period of time greater than one microsecond and the dopant from the dopant source is absorbed into the molten semiconductor. The semiconductor device includes a semiconductor material structure in which a junction is formed and may incorporate a multi-layer anti-reflection coating.Type: GrantFiled: February 11, 2010Date of Patent: September 15, 2015Assignee: NewSouth Innovations Pty LimitedInventors: Alison Maree Wenham, Ziv Hameiri, Ji Jing Jia, Ly Mai, Shi Zhengrong, Budi Tjahjono, Stuart Ross Wenham
-
Publication number: 20150253917Abstract: The present invention relates to a touch panel, a display panel, and a strengthened structure for a protective substrate, wherein the touch panel comprises: a touch sensing layer; a buffer layer disposed over the touch sensing layer and having a first surface and a second surface, wherein the second surface faces towards the touch sensing layer; and a protective substrate disposed on the first surface of the buffer layer.Type: ApplicationFiled: March 4, 2015Publication date: September 10, 2015Inventors: Chia-Fu FAN, Tsu-Hsien KU, Chia-Rung HSU, Jing-Jia YEH
-
Publication number: 20150198824Abstract: The present invention relates to a display, comprising: a first substrate comprising a first surface and a second surface opposite to the first surface; an edge surface adjacent to the first surface and the second surface, and comprising a side face and a first chamfer portion, wherein the first chamfer portion is disposed between the side face and the first surface; and a protective layer disposed on the first chamfer portion, and exposing at least a part of the side face.Type: ApplicationFiled: December 15, 2014Publication date: July 16, 2015Inventors: Jing-Jia YEH, Tsu-Hsien KU
-
Publication number: 20140322860Abstract: A method of depositing metal on an exposed surface of a p-type semiconductor region of a semiconductor device comprising a p-n junction is disclosed, the method comprising: immersing the exposed surface of the p-type semiconductor region on which the metal is to be deposited in a solution of metal ions; producing an electric field in the semiconductor device such that the p-n junction is forward biased; electrochemically depositing the metal on the exposed surface of the p-type semiconductor region of the semiconductor device by reduction of metal ions in the solution.Type: ApplicationFiled: November 12, 2012Publication date: October 30, 2014Applicant: NewSouth Innovations Pty LimitedInventors: Valantis Vais, Alison Joan Lennon, Stuart Ross Wenham, Jing Jia Ji, Alison Maree Wenham
-
Publication number: 20140251817Abstract: A method of forming an oxide layer on an exposed surface of a semiconductor device which contains a p-n junction is disclosed, the method comprising: immersing the exposed surface of the semiconductor device in an electrolyte; producing an electric field in the semiconductor device such that the p-n junction is forward-biased and the exposed surface is anodic; and electrochemically oxidising the exposed surface to form an oxide layer.Type: ApplicationFiled: May 23, 2014Publication date: September 11, 2014Applicant: NewSouth Innovations Pty LimitedInventors: Valantis Vais, Alison Joan Lennon, Stuart Ross Wenham, Jing Jia Ji, Alison Maree Wenham, Jingnan Tong, Xi Wang
-
Patent number: 8750616Abstract: In an extracting step, the extracting portion obtains a linked component composed of a plurality of mutually linking pixels from a character string region composed of a plurality of characters, and extracts section elements from the character string region, the section elements each being surrounded by a circumscribing figure circumscribing to the linked component. In the first altering step, the first altering portion combines section elements at least having a mutually overlapping part among the extracted section elements so as to prepare a new section element. In the first selecting step, the first selecting portion determines a reference size in advance and selects section elements having a size greater than the reference size, from among the section elements altered in the first altering step.Type: GrantFiled: December 21, 2007Date of Patent: June 10, 2014Assignee: Sharp Kabushiki KaishaInventors: Bo Wu, Jianjun Dou, Ning Le, Yadong Wu, Jing Jia