Abstract: A child carrier includes a frame, wheels disposed at the lower portion of the frame, a hand-pushed bar joined to the frame, a seat attachable to the frame by a fore swing arm and a rear swing arm. The fore swing arm and the rear swing arm are hinged respectively to the front and rear of the frame and are capable of swinging the seat. The child carrier further includes a switching device that permits a caregiver to adjust the distance between the lower ends of the fore and rear swing arms so that the seat can swing in a horizontal gliding motion or a pendulum type rocking motion. The carrier can also be used as a common hand-pushed carriage when the seat is fixed. The child carrier further includes an anti-swing latch capable of coupling the frame to the fore swing arm to prevent the seat from moving relative to the frame. The seat is adjustable to provide a forward or rearward facing stroller or carriage seat and is removable from the frame to provide a bassinet.

Abstract: Disclosed are a fixed-bed, catalytic reactor wherein reaction heat can be exchanged against a heat exchange medium circulating indirectly through the catalyst bed, and a catalytic process comprising operation of the reactor. The reactor comprises a catalyst bed having internally embedded banks of heat exchange tubes. An inlet distributor distributes reactants for flow through the bed. The distributed fluid passes through the bed in a flow path wherein a catalytic reaction occurs. The reaction effluent is then collected from the bed by an outlet product collector. A heat exchange medium circulated through the internal heat exchange tubes adds or removes reaction heat as required for enhanced conversion in the reactor. Multiple heat exchange tubes can be used, and inlet and discharge manifolds are provided for distributing the circulating heat exchange medium. The heat exchange tubes can be spaced in accordance with the heat interchange required to optimize the reaction rate.

Abstract: The present invention provides a unified image and graphics processing system that provides both image and graphics processing at high speeds. The system includes a parallel vector processing unit, a graphics subsystem, a shared memory and a set of high-speed data buses for connecting all of the other components. Generally, the parallel vector processing unit includes a series of vector processors. Each processor includes a vector address generator for efficient generation of memory addresses for regular address sequences. In order to synchronize and control the vector processors' accesses to shared memory, the parallel vector processing unit includes shared memory access logic. The logic is incorporated into each vector processor. The graphics subsystem includes a series of polygon processors in a pipelined configuration. Each processor is connected in the pipeline by a first-in-first-out (FIFO) buffer for passing data results.