Abstract: To increase the efficiency of electronic design automation, employ a first subset of integrated circuit patterning modeling data to generate weights of a neural network-based patterning model; employ a second subset of integrated circuit patterning modeling data to generate updated weights of the neural network-based patterning model, to obtain an updated neural network-based patterning model; evaluate the updated neural network-based patterning model; and responsive to the evaluating of the updated neural network-based patterning model being successfully completed, deploy the updated neural network-based patterning model.

Abstract: According to one or more embodiments of the present invention a computer-implemented method for fabricating a chip includes generating, using an aerial image generation system, a set of aerial images for a chip layout, the set of aerial images including an aerial image corresponding to each region from the chip layout. The method further includes automatically determining, using an artificial neural network, a feature vector for each aerial image from the set of aerial images. The method further includes clustering the aerial images using their corresponding feature vectors. The method further includes selecting, as test samples, a predetermined number of aerial images from each cluster. The method further includes performing a pattern coverage inspection of the chip layout using the aerial images that are selected as test samples.

Abstract: In accordance with an embodiment of the present invention, a photolithographic mask is provided. The photolithographic mask includes at least one merged via pattern in the photolithographic mask for printing a merged via opening in a resist layer, wherein the at least one merged via pattern includes a compound shape having a first rectangular opening portion and a second rectangular opening portion that intersect at an angle.

Abstract: The present invention discloses self-thickening compositions comprising one or more N-acyl acidic amino acid and/or a salts thereof and one or more amphoteric surfactant, methods of preparation thereof, and their applications in cosmetics and personal care, home care and other fields with excellent thickening performance and easy-to-use applicability, in particular in cleansing formulations to improve performance such as foam quality and mildness.

Abstract: A computer-implemented method, computer program product, a computer processing system are provided for generating synthetic via layout patterns by a Recurrent Neural Network (RNN). The method includes generating, by a processor, a training data set of coordinate arrays that specify coordinates of vias in a set of physical design layouts. The method further includes training, by the processor, the RNN with the training data set of coordinate arrays. The method also includes generating, by the processor, using the RNN, new synthetic via patterns.

Abstract: A method for predicting local layout effect in a circuit design pattern includes obtaining a plurality of circuit design patterns, generating layout images from the circuit design patterns, extracting feature vectors from the layout images by processing the layout images in a computer vision machine learning algorithm, comparing the feature vector extracted from a selected layout image to clusters of feature vectors extracted from the layout images, wherein the clusters of feature vectors include an in-range cluster and an outlier cluster, and labelling a circuit design pattern corresponding to the selected layout image, for which threshold voltage has not been experimentally measured, as being an in-range circuit design pattern or an outlier circuit design pattern, in response to the selected layout image respectively correlating with the in-range cluster or with the outlier cluster.

Abstract: A method for predicting local layout effect in a circuit design pattern includes obtaining a plurality of circuit design patterns, generating layout images from the circuit design patterns, extracting feature vectors from the layout images by processing the layout images in a computer vision machine learning algorithm, comparing the feature vector extracted from a selected layout image to clusters of feature vectors extracted from the layout images, wherein the clusters of feature vectors include an in-range cluster and an outlier cluster, and labelling a circuit design pattern corresponding to the selected layout image, for which threshold voltage has not been experimentally measured, as being an in-range circuit design pattern or an outlier circuit design pattern, in response to the selected layout image respectively correlating with the in-range cluster or with the outlier cluster.

Abstract: A method of co-optimizing lithographic and etching processes for semiconductor fabrication. The method includes determining a first set of locations for a first complementary laser annealing to be performed on. The first complementary laser annealing is performed at the first set of locations on at least a first semiconductor wafer of a plurality of semiconductor wafers. The first complementary laser annealing is performed before or after a first post-exposure baking process for the at least first semiconductor wafer. After an etching process has been performed on at least the first semiconductor wafer, a second set of locations is determined for a second complementary laser annealing to be performed on. The second complementary laser annealing is performed at the second set of locations on at least a second semiconductor wafer of the plurality of semiconductor wafers. The second complementary laser annealing is performed before or after a second post-exposure baking process.

Abstract: A method for generating physical design layout patterns includes selecting as training data one or more physical design layout patterns of integrated multi-layers for features in at least two layers of a given patterned structure. The method also includes converting the physical design layout patterns into three-dimensional arrays, a given three-dimensional array comprising a set of two-dimensional arrays each representing features of one layer of the layers in a given one of the physical design layout patterns. The method further includes training, utilizing the three-dimensional arrays, a generative adversarial network (GAN) comprising a discriminator neural network and a generator neural network. The method further includes generating synthetic three-dimensional arrays utilizing the generator neural network of the trained GAN, a given synthetic three-dimensional array comprising a set of two-dimensional arrays each representing features for a new layer of a new physical design layout pattern.

Abstract: A method for detecting hotspots in physical design layout patterns includes receiving a given physical design layout pattern, utilizing a hotspot detection model to detect one or more potential hotspots in the given physical design layout pattern, and performing a verification to determine whether a given potential hotspot of the one or more potential hotspots detected by the hotspot detection model comprises a real hotspot or a nonexistent hotspot. The method also includes, responsive to determining that the given potential hotspot comprises an actual hotspot, modifying the given physical design layout pattern to remove the actual hotspot. The method further includes, responsive to determining that the given potential hotspot comprises a nonexistent hotspot, augmenting the hotspot detection model with additional training data generated based on the nonexistent hotspot.

Abstract: A method for generating physical design layout patterns includes selecting as training data a set of physical design layout patterns of features in a given layer of a given patterned structure and converting the physical design layout patterns into two-dimensional (2D) arrays comprising entries for different locations in the given layer of the given patterned structure with values representing presence of the features at the different locations. The method also includes training, utilizing the 2D arrays, a generative adversarial network (GAN) comprising a discriminator neural network and a generator neural network. The method further includes generating one or more synthetic 2D arrays utilizing the trained generator neural network of the GAN, a given synthetic 2D array comprising entries for different locations in the given layer of a new physical design layout pattern with values representing presence of the features at the different locations of the new physical design layout pattern.

Abstract: A system, a computer program product, and method for physically fabricating an electronic circuit using design space exploration as part of a design process is described. The method begins with defining a plurality of design space parameters to be tuned along with parameter ranges for each of the plurality of design space parameters. Next an output target to be optimized is defined. A series of one or more test mask shapes are generated to appear on a photo mask using the plurality of design space parameters. A simulation of a post lithography or etch on the series of one or more test mask shapes is performed to produce simulation output values. Next, the simulation output values and corresponding design space parameters are fed into to a Bayesian inference algorithm for assessment and identification of a next combination of design space parameters to investigate.

Abstract: A computer-implemented method, computer program product, a computer processing system are provided for generating synthetic via layout patterns by a Recurrent Neural Network (RNN). The method includes generating, by a processor, a training data set of coordinate arrays that specify coordinates of vias in a set of physical design layouts. The method further includes training, by the processor, the RNN with the training data set of coordinate arrays. The method also includes generating, by the processor, using the RNN, new synthetic via patterns.

Abstract: A method of modeling distributions of post-lithography critical dimensions includes the following steps. A plurality of aerial images of respective portions of a physical design layout of a semiconductor wafer are generated, and the plurality of aerial images are employed as training data. In the method, first and second portions of a neural network architecture are generated. The first portion includes a neural network which is shared by a plurality of output channels, and the second portion includes a plurality of neural networks, wherein each of the plurality of neural networks respectively correspond to one of the plurality of output channels. The method further includes training the first and second portions of the neural network architecture with the training data, and outputting the distributions of the post-lithography critical dimensions based on the plurality of output channels.

Abstract: According to one or more embodiments of the present invention a computer-implemented method for fabricating a chip includes generating, using an aerial image generation system, a set of aerial images for a chip layout, the set of aerial images including an aerial image corresponding to each region from the chip layout. The method further includes automatically determining, using an artificial neural network, a feature vector for each aerial image from the set of aerial images. The method further includes clustering the aerial images using their corresponding feature vectors. The method further includes selecting, as test samples, a predetermined number of aerial images from each cluster. The method further includes performing a pattern coverage inspection of the chip layout using the aerial images that are selected as test samples.

Abstract: A method for detecting hotspots in physical design layout patterns includes receiving a given physical design layout pattern, utilizing a hotspot detection model to detect one or more potential hotspots in the given physical design layout pattern, and performing verification to determine whether a given one of the potential hotspots detected by the hotspot detection model comprises a real hotspot or a nonexistent hotspot. The method also includes, responsive to determining that the given potential hotspot comprises an actual hotspot, modifying the given physical design layout pattern to remove the actual hotspot. The method further includes, responsive to determining that the given potential hotspot comprises a nonexistent hotspot, augmenting the hotspot detection model with additional training data generated based on the nonexistent hotspot.

Abstract: Methods and systems for fabricating an integrated circuit include training a machine learning model using a training set that includes known physical design layout patterns that are classified according to whether the patterns include a hotspot. It is determined whether an input physical design layout pattern includes a hotspot using the machine learning model. A hotspot localization is generated for the input physical design layout patterns. The input physical design pattern is adjusted to cure the hotspot. A circuit is fabricated in accordance with the adjusted input physical design layout pattern.

Abstract: A method is presented for generating a plurality of physical design layout patterns. The method includes selecting one or more physical design layouts for neural network training, converting the plurality of physical design layout patterns into coordinate arrays, a coordinate array of the coordinate arrays including via center coordinates of vias in a physical design layout pattern of the plurality of physical design layout patterns, training, by employing the coordinate arrays, a variational autoencoder (VAE), and generating one or more new synthetic coordinate arrays by employing the trained VAE, a synthetic coordinate array of the one or more new synthetic coordinate arrays including via center coordinates of vias for a new physical design layout pattern.

Abstract: A system and method to perform risk assessment or design rule determination for an integrated circuit involves generating two or more process variation contours based on corresponding two or more combinations of two or more factors that affect manufacturability of the integrated circuit. Each of the two or more process variation contours is associated with a probability. The method also includes generating a random number to select from among the two or more process variation contours based on a cumulative probability value associated with each of the two or more process variation contours. The cumulative probability values are determined from the probabilities. The risk assessment or the design rule determination is performed using selected ones of the two or more process variation contours. Fabrication yield is increased based on finalizing the physical layout using the process variation contours.

Abstract: A method for generating physical design layout patterns includes the step of selecting one or more physical design layouts, a given physical design layout comprising a set of physical design layout patterns for features in at least one layer of a given patterned structure. The method also includes the step of converting the physical design layout patterns into coordinate arrays, a given coordinate array comprising feature center coordinates for the features in a given one of the physical design layout patterns. The method further includes the step of training, utilizing the coordinate arrays, a generative adversarial network (GAN) comprising discriminator and generator neural networks. The method further includes the step of generating one or more synthetic coordinate arrays utilizing the trained generator neural network of the GAN, a given one of the synthetic coordinate arrays comprising feature center coordinates of features for a new physical design layout pattern.