Abstract: An isotope analysis system includes: a first liquid channel, second liquid channels, third liquid channels, fourth liquid channels connected with a heating reactor, a diverter, and a selector valve. The diverter is configured to divert liquid from the first liquid channel to the third liquid channels. The selector valve comprises a first liquid outlet and a plurality of first liquid inlets. A third liquid channel and a fourth liquid channel are assigned to each of the plurality of second liquid channels; an end of the fourth liquid channel is connected to both an end of the second liquid channel and an end of the third liquid channel; and a first liquid inlet is assigned to each of the plurality of fourth liquid channels, and another end of the fourth liquid channel is connected to the first liquid inlet.

Abstract: Example memory devices, systems, and methods for reducing erase disturb in memory devices are disclosed. One example method includes erasing, during an erase operation of a block in a memory cell array, one or more memory cells in the block. It is verified, during the erase operation of the block, whether the one or more memory cells are erased. Each of one or more blocks in the memory cell array is respectively read during the erase operation of the block, where respectively reading each of the one or more blocks includes applying a first voltage to a first select gate line coupled to a first select gate transistor in the block, and applying a second voltage to a second select gate line coupled to a second select gate transistor in one of the one or more blocks, where the first voltage is lower than the second voltage.

Abstract: A superconducting magnet system for fusion reactor includes a superconducting magnet unit, an integrated power supply system and a quench diagnostic system. The superconducting magnet unit includes a superconducting coil module and a cryogenic refrigeration module. The superconducting coil module includes a toroidal field coil, a poloidal field coil and a centric solenoidal magnet module. The integrated power supply system includes a power supply module, a power supply monitoring module, and an alternating current (AC)/direct current (DC) power distribution module connected to the power supply module and the power supply monitoring module. The quench diagnostic system includes a resistive voltage diagnostic module, a distributed optical fiber diagnostic module and a voiceprint diagnostic module.

Abstract: Implementations of the present application provide a memory device, an operating method and a memory system. Here, the memory device includes: a memory cell array including at least one memory block; peripheral circuits coupled to the memory blocks and including a storage structure, wherein the peripheral circuit are configure to: receive and parse an operation command to obtain at least one address information; read, from the storage structure, the state information of the corresponding memory block to be operated according to each address information with the state information indicates whether the memory block is a bad block; and generate a stop signal in response to the state information of a memory block to be operated indicating that the memory block to be operated is a bad block, wherein the stop signal indicates to cease performing the operations on the memory block to be operated.

Abstract: A superconducting magnet system for fusion reactor includes a superconducting magnet unit, an integrated power supply system and a quench diagnostic system. The superconducting magnet unit includes a superconducting coil module and a cryogenic refrigeration module. The superconducting coil module includes a toroidal field coil, a poloidal field coil and a centric solenoidal magnet module. The integrated power supply system includes a power supply module, a power supply monitoring module, and an alternating current (AC)/direct current (DC) power distribution module connected to the power supply module and the power supply monitoring module. The quench diagnostic system includes a resistive voltage diagnostic module, a distributed optical fiber diagnostic module and a voiceprint diagnostic module.

Abstract: Example memory devices, systems, and methods for reducing erase disturb in memory devices are disclosed. One example method includes erasing, during an erase operation of a block in a memory cell array, one or more memory cells in the block. It is verified, during the erase operation of the block, whether the one or more memory cells are erased. Each of one or more blocks in the memory cell array is respectively read during the erase operation of the block, where respectively reading each of the one or more blocks includes applying a first voltage to a first select gate line coupled to a first select gate transistor in the block, and applying a second voltage to a second select gate line coupled to a second select gate transistor in one of the one or more blocks, where the first voltage is lower than the second voltage.

Abstract: Examples of the present disclosure provide a test device, a wafer, and a test method. The test device includes a control circuit connected to M groups of pads and N groups of test units, wherein M and N are both integers greater than 1; a number of test units included in each group of test units is less than or equal to M, and a total number of the test units is greater than M. The control circuit is configured to receive a test signal, select one of the N groups of test units based on the test signal, and connect at least some of the M groups of pads to the test units in the selected group of test units in one-to-one correspondence.

Abstract: Examples of the present application disclose memory devices, operating methods of memory devices, and memory systems. An example memory device includes: a memory cell array including: a first memory block; and a peripheral circuit coupled with the first memory block and configured to: receive a first block address information of the first memory block; determine whether the first memory block is a bad block according to the first block address information; generate a first indication signal in response to the first memory block being determined as the bad block; and stop activation of the first memory block pointed to by the first block address information in response to the first indication signal.

Abstract: Methods, systems, and apparatus for performing an erase operation in a memory system are described. An example system includes a memory device and a memory controller. The memory device includes a memory cell array and a peripheral circuit coupled to the memory cell array. Before applying an erase pulse to a source line coupled to the memory cell array, the peripheral circuit separately performs pre-programming operations on word lines and select gate lines of the memory cell array by performing a first pre-programing operation on word lines in a first time period and performing a second pre-programing operation on a first select gate line in a second time period.

Abstract: In certain aspects, a memory device includes an array of memory cells, word lines respectively coupled to rows of the memory cells, and a peripheral circuit coupled to the array of memory cells through the word lines and configured to read a select row of the rows of the memory cells. The peripheral circuit includes a word line driver coupled to the select row through a select word line of the word lines and to an unselect row of the rows of the memory cells through an unselect word line of the word lines, and configured to apply a pass voltage to the unselect word line, and discharge the unselect word line from the pass voltage to a first recovery voltage that is greater than a supply voltage of the array of memory cells.

Abstract: The present invention relates to a skin with protrusions on a surface, and a component with the skin for use in the interior of a vehicle. The present invention further relates to a forming method for the component. The present invention comprises: a base layer with an upper surface; and a plurality of microscopic protrusions spaced apart and distributed in at least a part of the area of the upper surface, which enables the upper surface of the base layer to be configured as a suede surface. The skin is formed by integrated injection molding of a material comprising a thermoplastic elastomer and a compatible resin.

Abstract: A power control method of a lower RF power supply of semiconductor processing equipment includes, when a processing chamber starts semiconductor processing, with a predetermined power compensation equation and according to a pre-obtained first RF circuit parameter set of a reference chamber and a second RF circuit parameter set of a present processing chamber performing the semiconductor processing, obtaining a power compensation coefficient of the present processing chamber relative to the reference chamber, according to the power compensation coefficient and a power setting value of the lower RF power supply of the present processing chamber, calculating a power compensation value of the present processing chamber relative to the reference chamber, and controlling the lower RF power supply to output the power compensation value.

Abstract: Example memory devices, systems, and methods for reducing erase disturb in memory devices are disclosed. One example method includes erasing, during an erase operation of a block in a memory cell array, one or more memory cells in the block. It is verified, during the erase operation of the block, whether the one or more memory cells are erased. Each of one or more blocks in the memory cell array is respectively read during the erase operation of the block, where respectively reading each of the one or more blocks includes applying a first voltage to a first select gate line coupled to a first select gate transistor in the block, and applying a second voltage to a second select gate line coupled to a second select gate transistor in one of the one or more blocks, where the first voltage is lower than the second voltage.

Abstract: An experimental system and a method for simulating a gear transmission of an electric multiple unit under wheel-rail excitation are provided. The experimental system includes a gear transmission experimental table and an excitation device. Under the action of the excitation device, the electric multiple unit gear transmission experimental table carries out no-load and load experiments of a gear transmission system to simulate the dynamic characteristic change of the gear transmission system under the wheel-rail excitation environment. The basic experiments of the gear transmission system of the electric multiple unit can be carried out, the wheel-rail excitation received by the gear transmission system during operation of the electric multiple unit can also be simulated, thus making up the vacancy of the experimental researches in the field of electric multiple unit transmission considering the environmental conditions of wheel-rail excitation in China.

Abstract: Aspects of the disclosure provide a memory device. For example, the memory device can include a memory array, a bit line and a buffer. The memory array can include a plurality of memory strings. The memory strings can be divided into a first memory string group and a second memory string group. The bit line can include a first bit line segment coupled to the first memory string group and a second bit line segment coupled to the second memory string group. The buffer can be coupled to the memory array by the bit line. The memory array and the buffer can be included in separate first and second dies, respectively, and the first die can be bonded to the second die.

Abstract: A method includes performing a programming operation on the memory cell using incremental step pulse programming. The programming operation includes applying one or more first voltage steps to the word line using a first step value to increase a threshold voltage of the memory cell toward a programming state. The programming operation also includes determining a quantity of memory cells that have a threshold voltage between first and second verification voltages. The second verification voltage is less than the first verification voltage and outside of a range of threshold voltages corresponding to the programming state. The programming operation also includes determining a step adjustment value based on the determining of the quantity. The programming operation also includes adjusting the first step value using the step adjustment value.

Abstract: The present disclosure provides memories, operation methods of memories, and memory systems. An example memory includes: a memory cell array, word lines, a first select line, and a peripheral circuit. The peripheral circuit is configured to: in a first period of a recovery period of a verify operation, apply a first voltage to a first word line, and apply a second voltage to a second word line, wherein the second voltage is greater than the first voltage; in a second period of the recovery period of the verify operation, apply a third voltage to the first select line; and in a third period of the recovery period of the verify operation, apply a fourth voltage to the first word line, and apply a fifth voltage to the second word line, wherein the fifth voltage is greater than the fourth voltage.

Abstract: The present disclosure provides a power adjustment method of an upper electrode power supply of a semiconductor process apparatus. The method includes obtaining a processing load of an upper electrode power supply of a reference process chamber and a processing load of an upper electrode power supply of a current process chamber corresponding to semiconductor process step, when starting to perform a semiconductor process step, determining a power compensation coefficient for the current process chamber relative to the reference process chamber based on the processing load of the current process chamber and the processing load the reference process chamber, and controlling the upper electrode power supply to output compensation power. The compensation power is a product of the set power of the upper electrode power supply of the current process chamber corresponding to the semiconductor process step and the corresponding power compensation coefficient.

Abstract: The present disclosure provides an impedance-matching method applied to a semiconductor process apparatus, an impedance-matching device, and the semiconductor process apparatus. The impedance-matching method includes adjusting a parameter value of an adjustable element of an impedance-matching device to a preset initial value at beginning of a process, when a radio frequency (RF) power supply is powered on, adjusting the parameter value of the adjustable element according to a pre-stored optimal matching path corresponding to the process, and adjusting the parameter value of the adjustable element using an automatic matching algorithm after reaching end time of the preset matching period until impedance-matching is achieved. The optimal matching path includes parameter values of the adjustable element corresponding to different moments in a preset matching period.

Abstract: Examples of the present application provide a memory, an operation method thereof and a memory system, and relate to, but are not limited to, the field of storage technology. The memory includes a peripheral circuit, a plurality of word lines and a plurality of rows of memory cells. Each row of the memory cells is coupled with one word line. The peripheral circuit is configured to apply a first voltage to a first word line of the plurality of word lines in each of a plurality of first time periods. A second voltage is applied to the first word line in a second time period between every two adjacent ones of the plurality of first time periods, wherein the second voltage is configured to turn on the memory cells coupled with the first word line. As such, the accuracy of data reading can be improved.