Abstract: Embodiments provide a method for fabricating a semiconductor structure and a semiconductor structure. The method includes: providing a substrate having a plurality of active area; forming a plurality of bit lines arranged at intervals on the substrate, the plurality of bit lines having a plurality of first mask layers; forming a first dielectric layer on the substrate positioned between adjacent two of the plurality of bit lines; patterning the first dielectric layer, to form a plurality of first notches arranged at intervals on the first dielectric layer; forming a second mask layer on the first dielectric layer, and the second mask layer encircling in each of the plurality of first notches to form a second notch; forming a plurality of contact holes arranged at intervals in the first dielectric layer; and forming a conductive plunger in each of the plurality of contact holes.

Abstract: A manufacturing method of a semiconductor structure is provided, and the manufacturing method includes the following operations. A first trench is formed on the semiconductor substrate, in which the first trench penetrates at least two of the conductive channels of a transistor, at least part of each of the conductive channels is located at the bottom of the first trench, an oxide layer is provided between two adjacent ones of the conductive channels, and each of the conductive channels has a bump structure in the first trench relative to the oxide layer. The shape of the bump structure of each of the conductive channels at the bottom of the first trench is adjusted by etching at the bottom of the first trench, so that the bump structure has at least two protrusions. A gate structure is formed in the first trench.

Abstract: Embodiments disclose a buried bit line structure, a method for fabricating the buried bit line structure, and a memory. The buried bit line structure includes: a substrate having a bit line trench; a bit line metal filled in the bit line trench; and a bit line contact filled in the bit line trench and positioned on the bit line metal, where an arc-shaped contact surface is provided between the bit line contact and the bit line metal. By setting a contact surface between the bit line contact and the bit line metal to be the arc-shaped contact surface, a contact area between the bit line contact and the bit line metal is increased, electrical conductivity of the bit line structure is enhanced.

Abstract: A method for manufacturing a semiconductor structure includes: providing a substrate and multiple spaced active areas on the substrate and an isolation structure between the adjacent active areas, in which, each of active areas includes multiple sub-active areas which intersect the initial bit line, and an initial bit line is provided on the substrate; patterning the active areas, the isolation structure and the initial bit line to form a word line trench located within the sub-active areas, the isolation structure, and the initial bit line, in which the remaining initial bit line serves as a bit line; forming a gate dielectric layer located on surfaces of the sub-active areas exposed by the word line trench; forming a word line and an insulating structure between the word line and the bit line, in which the word line is located on the gate dielectric layer and fills the word line trench.

Abstract: The disclosure relates to the technical field of semiconductors, and to a memory, a semiconductor structure and a method for same. The method includes: providing a substrate, the substrate including a plurality of conductive contact plugs in array distribution and insulation layers separating the conductive contact plugs; and forming a plurality of capacitive layers stacked and distributed in a direction perpendicular to the substrate on a surface of the substrate, each of the capacitive layers including a plurality of capacitances distributed at intervals, and the capacitances being respectively connected to different conductive contact plugs. According to the method, the storage capacity of capacitances can be increased, and product yield can be enhanced.

Abstract: The present disclosure provides a semiconductor memory device and a manufacturing method thereof. The manufacturing method includes: providing a substrate having a plurality of active areas; forming a plurality of bit line structures on the substrate, where the plurality of bit line structures are sequentially provided at intervals along a first direction; forming a dielectric layer on the substrate; etching the dielectric layer, to form a plurality of contact holes and a plurality of isolation structures, where each contact hole is between the adjacent bit line structures, the plurality of contact holes and the plurality of isolation structures are alternately provided along a second direction, the first direction is not parallel to the second direction; and forming an isolation layer on a side wall of each bit line structure and a side wall of each isolation structure.

Abstract: Embodiments of the present application relate to the field of semiconductors, and provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate, including active regions arranged at intervals and an isolation structure located between the active regions; a word line (WL) trench, penetrating through the active region and the isolation structure along a first direction; and a WL, located in the WL trench, wherein on a section in a second direction, a first height difference is formed between the active region and the isolation structure; and the second direction is parallel to the substrate and perpendicular to the first direction.

Abstract: The present disclosure provides a semiconductor device, a method of manufacturing a semiconductor device and an electronic device. The method of manufacturing a semiconductor device includes: forming word line trenches on a semiconductor substrate, forming a word line structure in each of the word line trenches, and finally forming active regions. The word line trenches pass through the semiconductor substrate without passing through other material.

Abstract: Embodiments of the present application relate to the field of semiconductors, and provide a manufacturing method of a semiconductor structure and a structure thereof. The method of manufacturing a semiconductor structure includes: providing a substrate, active regions and an isolation structure; patterning the active regions and the isolation structure to form a word line trench, sidewalls of the word line trench exposing the active regions and the isolation structure; performing corner rounding at least once on the active regions and the isolation structure exposed by the sidewalls of the word line trench, such that a first height difference is formed between remaining active regions and the isolation structure, wherein the corner rounding includes: etching the isolation structure exposed by the sidewalls of the word line trench, such that a first thickness of the active regions are exposed by the isolation structure.

Abstract: A semiconductor structure and a method of manufacturing the same are provided. The semiconductor structure includes a substrate, bit line structures and isolation walls located on side walls of the bit line structures, and capacitor contact holes. In the substrate, conductive contact regions are arranged. The conductive contact regions are exposed from the substrate. A plurality of discrete bit line structures are located on the substrate. Each of the isolation walls includes at least one isolation layer and a gap between the isolation layer and the bit line structure. Each of the capacitor contact holes is constituted by a region surrounded by the isolation walls between the adjacent bit line structures. The capacitor contact holes expose the conductive contact regions. A top width of the capacitor contact holes is larger than a bottom width thereof in a direction parallel to an arrangement direction of the bit line structures.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure. The method of manufacturing a semiconductor structure includes: providing a base, wherein the base includes an active region and a shallow trench isolation structure separating the active region, a word line trench is formed in the base, and the word line trench exposes a part of the active region and the shallow trench isolation structure; forming a first intermediate structure in the word line trenches, wherein the first intermediate structure covers side walls and a bottom wall of the word line trench, a first trench is formed in the first intermediate structure, the first intermediate structure includes a sacrificial structure, and the sacrificial structure includes a horizontal portion; and removing the horizontal portion of the sacrificial structure, and closing the first trench, and forming an air chamber.

Abstract: A forming method of a semiconductor structure includes the following: providing a semiconductor substrate formed with a first mask layer having a preset pattern; forming a second mask layer having a first mask pattern on a surface of the first mask layer, wherein the first mask pattern includes a plurality of first sub-patterns arranged in sequence; forming a second mask pattern in the second mask layer through the first mask pattern in a self-alignment manner, wherein the second mask pattern includes the first sub-patterns of the first mask pattern and second sub-patterns corresponding to the first sub-patterns; etching the first mask layer based on the first sub-patterns and the second sub-patterns of the second mask pattern to convert the preset pattern into an active area pattern; and defining active areas in the semiconductor substrate based on the active area pattern.

Abstract: Provided are a memory and a method for manufacturing the same, and relates to the technical field of semiconductors. The manufacturing method of a memory comprises: providing a substrate; forming a plurality of sacrificial pillars arranged at intervals between each two adjacent ones of the bit line isolation walls; forming a supplementary layer on surfaces of the sacrificial pillars; performing ion implantation to the supplementary layer; etching the supplementary layer; forming insulating pillars between adjacent sacrificial pillars; removing the sacrificial pillars and the remaining supplementary layer; and forming a plurality of node contact plugs in the contact holes.

Abstract: The present application provides a manufacturing method of a semiconductor structure, and relates to the technical field of semiconductors. The manufacturing method includes: providing a substrate; and forming multiple spaced first isolation sidewall structures on the substrate, where first opening regions are formed between adjacent first isolation sidewall structures, and each of the first opening regions is used to expose at least two columns of active regions.

Abstract: An information processing device 1X mainly includes an overall fatigue acquisition means 15B, a physical fatigue acquisition means 16B, and a mental fatigue calculation means 17B. The overall fatigue acquisition means 15B is configured to acquire an overall fatigue degree Ft which indicates a degree of overall fatigue of an object person. The physical fatigue acquisition means 16B is configured to acquire a physical fatigue degree Fp which indicates a degree of physical fatigue of the object person. The mental fatigue calculation means 17B is configured to calculate a mental fatigue degree which indicate a degree of mental fatigue of the object person based on the overall fatigue degree Ft and the physical fatigue degree Fp.

Abstract: The embodiments of the present disclosure belong to the field of semiconductor manufacturing technology and relates to a method for manufacturing a semiconductor structure and a semiconductor structure. The method for manufacturing the semiconductor structure includes: a bit line structure is formed on a substrate, a fill channel is formed between the insulating structures on two adjacent bit lines; a conductor is formed within the fill channel; at least one slit is formed on the conductor along a direction perpendicular to a longitudinal direction of each of the plurality of bit line to divide the conductor into a plurality of conductive blocks, each of the plurality of conductive blocks is connected to one of transistors on the substrate.

Abstract: The present disclosure provides a method of manufacturing a buried bit line structure and a buried bit line structure. The method of manufacturing a buried bit line structure includes: providing an initial structure, the initial structure including active region structures; forming an initial bit line trench, the initial bit line trench exposing the active region structure; forming a conductive structure, the conductive structure being located at the bottom of the initial bit line trench; forming a bit line contact structure, the bit line contact structure covering the conductive structure, and a top surface of the bit line contact structure being lower than a top surface of the active region structure; and forming an insulation structure, the insulation structure covering the bit line contact structure.

Abstract: A semiconductor manufacturing method includes: providing a semiconductor substrate, in which the semiconductor substrate includes an array region and a peripheral circuit region, in the array region, multiple capacitor contact holes are on the semiconductor substrate, and a first conductive layer is deposited on a bottom of each of the capacitor contact hole, and in the peripheral circuit region, a device layer is on the semiconductor substrate; treating the first conductive layer to increase its roughness; forming wire contact holes exposing the semiconductor substrate in the peripheral circuit region; forming a transition layer that at least covers a surface of the first conductive layer and a surface of the semiconductor substrate exposed by the wire contact holes; and forming a second conductive layer that covers the transition layer, and fills the capacitor contact holes and the wire contact holes.

Abstract: The disclosure relates to a semiconductor storage device and a forming method thereof. The semiconductor storage device includes a substrate; a plurality of active region structures provided on the substrate; a shallow trench isolation structure provided within the substrate, the shallow trench isolation structure surround the plurality of active region structures; a plurality of conductive line structures, extending parallel to each other along a first direction, the conductive line structure include a first region and a second region, the first region being located over each of the plurality of active region structures, the second region is located over the shallow trench isolation structure; in a direction perpendicular to the substrate, the depth of the first region is greater than the depth of the second region.

Abstract: This disclosure relates to crystalline forms of 3-{4-[(2R)-2-aminopropoxy]phenyl}-N-[(1R)-1-(3-fluorophenyl) ethyl]imidazo[1,2-b]pyridazin-6-amine and its salts, as well as methods of preparing and using such crystalline forms.