Abstract: A method of forming a semiconductor device comprising the following sequential steps. A substrate having a gate electrode stack formed thereover is provided. The substrate having an exposed surface and the gate electrode stack including a lower portion with exposed side walls. A first oxide layer is formed over: the exposed side walls of the lower portion of the gate electrode stack; and the exposed surface of the substrate. A conformal dielectric layer is formed over the gate electrode stack and the first oxide layer. A sacrificial dielectric layer is formed over the conformal dielectric layer. The horizontal portions of the sacrificial dielectric layer, the conformal dielectric layer and the underlying portions of the first oxide layer are patterned to form: sacrificial dielectric spacers; L-shaped conformal dielectric spacers thereunder; and L-shaped first oxide layer spacers thereunder.

Abstract: A method of forming metal lines is disclosed. The method comprises forming a metal layer over a semiconductor substrate. A hard mask layer is then formed over the metal layer. The hard mask layer is then patterned and etched with a pattern corresponding to the desired metal line pattern. Sidewall spacers are then formed on the sidewalls of the hard mask layer. Finally, the metal layer is etched using the hard mask layer and sidewall spacers as a mask.

Abstract: A process for forming a contact structure of a semiconductor device includes the steps of (a) providing a substrate having a plurality of gates thereon and a first oxide layer formed between the gates, (b) forming a first dielectric layer on the oxide layer and the gates, (c) forming a second oxide layer on the first dielectric layer, and (d) removing a portion of the second oxide layer for forming first spacers alongside each of the gates.

Abstract: A simplified method for forming a self-aligned contact hole is disclosed. The method comprises the steps of (a) providing a semiconductor substrate having a gate electrode and a diffusion region thereon; (b) forming a conformal layer of etch barrier material overlying the substrate surface including the diffusion region and the upper surface and the sidewalls of the gate electrode; (c) forming an insulating layer overlying the barrier layer; (d) etching an opening through the insulating layer self-aligned and borderless to the diffusion region by using the barrier layer as an etch stop; and (e) anisotropically etching the barrier layer underneath the opening, thereby exposing the diffusion region and simultaneously forming a spacer of the etch barrier material on the sidewall of the gate electrode.