Patents by Inventor Jing-Yang Jou
Jing-Yang Jou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20110153709Abstract: A compressor tree synthesis algorithm, named DOCT, which guarantees the delay optimal implementation in LUT-based FPGAs. Given a targeted K-input LUT architecture, DOCT firstly derives a finite set of prime patterns as essential building blocks. Then, it shows that a delay optimal compressor tree can always be constructed by those derived prime patterns via integer linear programming (ILP). Without loss of delay optimality, a post-processing procedure is invoked to reduce the number of demanded LUTs for the generated compressor tree design. DOCT has been evaluated over a broad set of benchmark circuits. The DOCT reduces the depth of the compressor tree and the number of LUTs based on the modern 8-input LUT-based FPGA architecture.Type: ApplicationFiled: March 4, 2010Publication date: June 23, 2011Inventors: Juinn-Dar HUANG, Jhih-Hong Lu, Bu-Ching Lin, Jing-Yang Jou
-
Patent number: 7577780Abstract: A fine-grained bandwidth control arbiter manages the shared bus usage of the requests of the masters which have real-time and/or bandwidth requirements, moreover, the masters are preset a ticket respectively. The arbiter consists of three components, a real-time handler, a bandwidth regulator, and a lottery manager with tuned weight. The real-time handler grants the most urgent request. The bandwidth regulator handles the bandwidth allocation and blocks the requests of masters that have met the bandwidth requirement. The lottery manager with tuned weight stochastically grants one of the contending masters according to the ticket assignment.Type: GrantFiled: February 28, 2007Date of Patent: August 18, 2009Assignee: National Chiao Tung UniversityInventors: Juinn-Dar Huang, Bu-Ching Lin, Geeng-Wei Lee, Jing-Yang Jou
-
Patent number: 7571414Abstract: A multi-project system-on-chip bench by integrating multiple system-on-chip projects into a chip, which uses a system chip bench, therefore, microprocessor, bus, embedded memory, peripheral component and input/output port is used together by those system-on-chip projects and the average cost of each system-on-chip is thus reduced. Moreover, this invention proposes a design method for multi-project system-on-chip bench, it let the user can effectively manage available data and verification environment in each design process flow hierarchy and in turn an easy-to-use design process flow is thus derived.Type: GrantFiled: June 15, 2006Date of Patent: August 4, 2009Assignee: National Chip Implementation Center, National Applied Research LaboratoriesInventors: Chun-Ming Huang, Chih-Chyau Yang, Jing-Yang Jou, Kuen-Jong Lee, Lan-Da Van
-
Publication number: 20080209093Abstract: A fine-grained bandwidth control arbiter manages the shared bus usage of the requests of the masters which have real-time and/or bandwidth requirements, moreover, the masters are preset a ticket respectively. The arbiter consists of three components, a real-time handler, a bandwidth regulator, and a lottery manager with tuned weight. The real-time handler grants the most urgent request. The bandwidth regulator handles the bandwidth allocation and blocks the requests of masters that have met the bandwidth requirement. The lottery manager with tuned weight stochastically grants one of the contending masters according to the ticket assignment.Type: ApplicationFiled: February 28, 2007Publication date: August 28, 2008Inventors: Juinn-Dar Huang, Bu-Ching Lin, Geeng-Wei Lee, Jing-Yang Jou
-
Publication number: 20070294658Abstract: A multi-project system-on-chip bench by integrating multiple system-on-chip projects into a chip, which uses a system chip bench, therefore, microprocessor, bus, embedded memory, peripheral component and input/output port is used together by those system-on-chip projects and the average cost of each system-on-chip is thus reduced. Moreover, this invention proposes a design method for multi-project system-on-chip bench, it let the user can effectively manage available data and verification environment in each design process flow hierarchy and in turn an easy-to-use design process flow is thus derived.Type: ApplicationFiled: June 15, 2006Publication date: December 20, 2007Inventors: Chun-Ming Huang, Chih-Chyau Yang, Jing-Yang Jou, Kuen-Jong Lee, Lan-Da Van
-
Patent number: 7013457Abstract: A computer system has an input system and an output system. Program code to be debugged has a plurality of program code statements. The input system is utilized to indicate an error variable in the program code. The error variable has an error value that differs from a desired value. An error set of the error variable is obtained, which is a subset of the statements in the computer readable code. Each statement in the error set is relationally connected to the error variable. A priority value is given to each statement in the error set. The priority values indicate a computed probability that the associated statement is an error source of the error variable. Finally, the output system is used to present each statement in the error set in an ordered manner according to the priority values.Type: GrantFiled: July 26, 2001Date of Patent: March 14, 2006Assignee: Springsoft, Inc.Inventors: Tai-Ying Chiang, Jing-Yang Jou, Ming-Chih Lai, Jien-Shen Tsai
-
Publication number: 20040205717Abstract: A computer system has an input system and an output system. Program code to be debugged has a plurality of program code statements. The input system is utilized to indicate an error variable in the program code. The error variable has an error value that differs from a desired value. An error set of the error variable is obtained, which is a subset of the statements in the computer readable code. Each statement in the error set is relationally connected to the error variable. A priority value is given to each statement in the error set. The priority values indicate a computed probability that the associated statement is an error source of the error variable. Finally, the output system is used to present each statement in the error set in an ordered manner according to the priority values.Type: ApplicationFiled: July 26, 2001Publication date: October 14, 2004Inventors: Tai-Ying Chiang, Jing-Yang Jou, Ming-Chih Lai, Jien-Shen Tsai
-
Patent number: 6675337Abstract: A built-in verification circuit having a circuit-under-test circuit, a test pattern generator, a bi-directional signal flow switch and three unidirectional, signal flow switches. The test pattern generator produces a testing pattern based on an input/output port order fault model. The bi-directional signal flow switch is positioned between the input terminal of the built-in verification circuit and the circuit-under-test circuit. The first unidirectional signal flow switch is positioned between the circuit-under-test circuit and the test pattern generator. The second unidirectional signal flow switch is positioned between the circuit-under-test circuit and the output terminal of the built-in verification circuit. The third unidirectional signal flow switch is positioned between the test pattern generator and the output terminal of the built-in verification circuit.Type: GrantFiled: August 2, 2000Date of Patent: January 6, 2004Assignee: Industrial Technology Research InstituteInventors: Shing-Wu Tung, Chun-Yao Wang, Jing-Yang Jou
-
Patent number: 5710711Abstract: A method and apparatus are taught which modify digital integrated circuits for partial scan testing and do so with little or no impact on the circuit's performance characteristics. Illustratively, the scan memory elements are selected from among all memory elements in a circuit based on their ability to eliminate feedback cycles in the circuit and on considerations of the potential performance degradation due to the inclusion of scan memory elements. A feedback cycle is defined as a feedback path from the output of a memory element to the input of said memory element.Type: GrantFiled: October 30, 1995Date of Patent: January 20, 1998Assignee: Lucent Technologies Inc.Inventors: Kwang-Ting Cheng, Jing-Yang Jou
-
Patent number: 4768196Abstract: Built-in self-test programmable logic arrays use a deterministic test pattern generator to generate test patterns such that each cross point in an AND-plane can be evaulated sequentially. A multiple input signature register which uses X.sup.Q +1 as its characteristic polynomial is used to evaulate the test results, where Q is the number of outputs. The final signature can be further compressed into only one bit. Instead of only determining the probability of fault detection, in this scheme, the fault detection capability has been analyzed using both the stuck at fault and the contact fault model. It can be shown that all of these faults can be detected. Shorts between two adjacent lines can be detected by using NOR gates.Type: GrantFiled: October 28, 1986Date of Patent: August 30, 1988Assignee: Silc Technologies, Inc.Inventors: Jing-Yang Jou, Christopher Rosebrugh