Patents by Inventor Jing-Yi Lee

Jing-Yi Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11957064
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.
    Type: Grant
    Filed: October 18, 2022
    Date of Patent: April 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
  • Publication number: 20240081157
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.
    Type: Application
    Filed: November 6, 2023
    Publication date: March 7, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
  • Publication number: 20240074328
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Applicant: United Microelectronics Corp.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
  • Patent number: 10512625
    Abstract: A topical pharmaceutical composition containing diacerein and/or its analogs is provided. Also provided is a method for treating various diseases using this topical pharmaceutical composition.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: December 24, 2019
    Assignee: TWI BIOTECHNOLOGY, INC.
    Inventors: Chih-Kuang Chen, Jing-Yi Lee, Wei-Shu Lu, Carl Oscar Brown, III
  • Patent number: 10474026
    Abstract: A method of correcting a layout pattern is provided in the present invention. The method includes the following steps. A layout pattern including at least two adjacent rectangular sub patterns is provided. The layout pattern is then input into a computer system. An optical proximity correction including a bevel correction is then performed. The bevel correction includes forming a bevel at a corner of at least one of the two adjacent rectangular sub patterns, wherein the bevel is formed by chopping the corner, and moving the bevel toward an interaction of two neighboring segments of the bevel if a distance between the bevel and the other rectangular sub pattern is larger than a minimum value. The angle between a surface of the bevel and a surface of the rectangular sub pattern is not rectangular. The layout pattern is output to a mask after the optical proximity correction.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: November 12, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuei-Hsu Chou, Cheng-Te Wang, Yung-Feng Cheng, Jing-Yi Lee
  • Publication number: 20190105296
    Abstract: A topical pharmaceutical composition containing diacerein and/or its analogs is provided. Also provided is a method for treating various diseases using this topical pharmaceutical composition.
    Type: Application
    Filed: December 6, 2018
    Publication date: April 11, 2019
    Inventors: Chih-Kuang Chen, Jing-Yi Lee, Wei-Shu Lu, Carl Oscar Brown, III
  • Patent number: 10195170
    Abstract: Methods and compositions for inhibiting expression of ASC, expression of NLRP3, and/or formation of NLRP3 inflammasome complex by using diacerein or its analogs are provided. Also provided are methods and compositions for the treatment and/or prevention of a disorder mediated by ASC and/or NLRP3, and/or by formation of NLRP3 inflammasome complex by using diacerein or its analogs.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: February 5, 2019
    Assignee: TWI Biotechnology, Inc.
    Inventors: Chih-Kuang Chen, Jing-Yi Lee, Wei-Shu Lu, Carl Oscar Brown, III
  • Patent number: 10154984
    Abstract: A topical pharmaceutical composition containing diacerein and/or its analogs is provided. Also provided is a method for treating various diseases using this topical pharmaceutical composition.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: December 18, 2018
    Assignee: TWi Biotechnology, Inc.
    Inventors: Chih-Kuang Chen, Jing-Yi Lee, Wei-Shu Lu, Carl Oscar Brown, III
  • Publication number: 20180120693
    Abstract: A method of correcting a layout pattern is provided in the present invention. The method includes the following steps. A layout pattern including at least two adjacent rectangular sub patterns is provided. The layout pattern is then input into a computer system. An optical proximity correction including a bevel correction is then performed. The bevel correction includes forming a bevel at a corner of at least one of the two adjacent rectangular sub patterns, wherein the bevel is formed by chopping the corner, and moving the bevel toward an interaction of two neighboring segments of the bevel if a distance between the bevel and the other rectangular sub pattern is larger than a minimum value. The angle between a surface of the bevel and a surface of the rectangular sub pattern is not rectangular. The layout pattern is output to a mask after the optical proximity correction.
    Type: Application
    Filed: October 27, 2016
    Publication date: May 3, 2018
    Inventors: Kuei-Hsu Chou, Cheng-Te Wang, Yung-Feng Cheng, Jing-Yi Lee
  • Publication number: 20180021290
    Abstract: A topical pharmaceutical composition containing diacerein and/or its analogs is provided. Also provided is a method for treating various diseases using this topical pharmaceutical composition.
    Type: Application
    Filed: July 25, 2017
    Publication date: January 25, 2018
    Inventors: Chih-Kuang Chen, Jing-Yi Lee, Wei-Shu Lu, Carl Oscar Brown, III
  • Publication number: 20170319532
    Abstract: A method of treating and/or preventing blood-associated disorders is provided. Also provided is a method of treating and/or preventing hemophilic arthropathy and/or hemochromatosis arthropathy in a subject.
    Type: Application
    Filed: May 5, 2017
    Publication date: November 9, 2017
    Inventors: Chih-Kuang Chen, Jing-Yi Lee, Wei-Shu Lu, Carl Oscar Brown, III
  • Patent number: 9785046
    Abstract: The present invention provides a pattern verifying method. First, a target pattern is decomposed into a first pattern and a second pattern. A first OPC process is performed for the first pattern to form a first revised pattern, and a second OPC process is performed for the second pattern to form a second revised pattern. An inspection process is performed, wherein the inspection process comprises an after mask inspection (AMI) process, which comprises considering the target pattern, the first pattern and the second pattern.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: October 10, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Te-Hsien Hsieh, Ming-Jui Chen, Cheng-Te Wang, Jing-Yi Lee, Jian-Yuan Ma, Yan-Chun Chen
  • Patent number: 9747404
    Abstract: A method for optimizing an integrated circuit layout design includes the following steps. A first integrated circuit layout design including a metal line feature having several metal lines and a second integrated circuit layout design including a hole feature having several holes are obtained. A line-end hole feature of the hole feature is selected by piecing the metal line feature with the hole feature. The line-end hole feature is classified into a single hole feature and a redundant hole feature by spacings between the adjacent holes by a computer system.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: August 29, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Ming Kuo, Ming-Jui Chen, Te-Hsien Hsieh, Ping-I Hsieh, Jing-Yi Lee, Yan-Chun Chen
  • Patent number: 9744131
    Abstract: A topical pharmaceutical composition containing diacerein and/or its analogs is provided. Also provided is a method for treating various diseases using this topical pharmaceutical composition.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: August 29, 2017
    Assignee: TWi Biotechnology, Inc.
    Inventors: Chih-Kuang Chen, Jing-Yi Lee, Wei-Shu Lu, Carl Oscar Brown, III
  • Publication number: 20170049733
    Abstract: Methods and compositions for inhibiting expression of ASC, expression of NLRP3, and/or formation of NLRP3 inflammasome complex by using diacerein or its analogs are provided. Also provided are methods and compositions for the treatment and/or prevention of a disorder mediated by ASC and/or NLRP3, and/or by formation of NLRP3 inflammasome complex by using diacerein or its analogs.
    Type: Application
    Filed: August 17, 2016
    Publication date: February 23, 2017
    Inventors: Chih-Kuang Chen, Jing-Yi Lee, Wei-Shu Lu, Carl Oscar Brown, III
  • Publication number: 20170024506
    Abstract: A method for optimizing an integrated circuit layout design includes the following steps. A first integrated circuit layout design including a metal line feature having several metal lines and a second integrated circuit layout design including a hole feature having several holes are obtained. A line-end hole feature of the hole feature is selected by piecing the metal line feature with the hole feature. The line-end hole feature is classified into a single hole feature and a redundant hole feature by spacings between the adjacent holes by a computer system.
    Type: Application
    Filed: July 23, 2015
    Publication date: January 26, 2017
    Inventors: Shih-Ming Kuo, Ming-Jui Chen, Te-Hsien Hsieh, Ping-I Hsieh, Jing-Yi Lee, Yan-Chun Chen
  • Publication number: 20170000732
    Abstract: A topical pharmaceutical composition containing diacerein and/or its analogs is provided. Also provided is a method for treating various diseases using this topical pharmaceutical composition.
    Type: Application
    Filed: June 30, 2016
    Publication date: January 5, 2017
    Inventors: Chih-Kuang Chen, Jing-Yi Lee, Wei-Shu Lu, Carl Oscar Brown, III
  • Publication number: 20160147140
    Abstract: The present invention provides a pattern verifying method. First, a target pattern is decomposed into a first pattern and a second pattern. A first OPC process is performed for the first pattern to form a first revised pattern, and a second OPC process is performed for the second pattern to form a second revised pattern. An inspection process is performed, wherein the inspection process comprises an after mask inspection (AMI) process, which comprises considering the target pattern, the first pattern and the second pattern.
    Type: Application
    Filed: January 21, 2015
    Publication date: May 26, 2016
    Inventors: Te-Hsien Hsieh, Ming-Jui Chen, Cheng-Te Wang, Jing-Yi Lee, Jian-Yuan Ma, Yan-Chun Chen
  • Patent number: 9262820
    Abstract: A method for IC design is provided. Firstly, an IC design layout having a main feature with an original margin is received. Then, a first modified margin of the main feature is generated; and a first photolithography simulation procedure of the main feature with the first modified margin is performed to generate a first contour having a plurality of curves. Next, an equation of each of the curves is obtained; each equation of the curves is manipulated to obtain a vertex of each of the curves. After that, a first group of target points are assigned to the original margin. Each of the first group of target points respectively corresponds to one of the vertices. Finally, an optical proximity correction (OPC) procedure is performed by using the first group of target points to generate a second modified margin. An apparatus for IC design is also provided.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: February 16, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Te-Hsien Hsieh, Ming-Jui Chen, Cheng-Te Wang, Jing-Yi Lee
  • Publication number: 20150332449
    Abstract: A method for IC design is provided. Firstly, an IC design layout having a main feature with an original margin is received. Then, a first modified margin of the main feature is generated; and a first photolithography simulation procedure of the main feature with the first modified margin is performed to generate a first contour having a plurality of curves. Next, an equation of each of the curves is obtained; each equation of the curves is manipulated to obtain a vertex of each of the curves. After that, a first group of target points are assigned to the original margin. Each of the first group of target points respectively corresponds to one of the vertices. Finally, an optical proximity correction (OPC) procedure is performed by using the first group of target points to generate a second modified margin. An apparatus for IC design is also provided.
    Type: Application
    Filed: May 19, 2014
    Publication date: November 19, 2015
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Te-Hsien HSIEH, Ming-Jui CHEN, Cheng-Te WANG, Jing-Yi LEE