Abstract: A device includes a first buried layer over a substrate, a second buried layer over the first buried layer, a first well over the first buried layer and the second buried layer, a first high voltage well, a second high voltage well and a third high voltage well extending through the first well, wherein the second high voltage well is between the first high voltage well and the third high voltage well, a first drain/source region in the first high voltage well, a first gate electrode over the first well, a second drain/source region in the second high voltage well and a first isolation region in the second high voltage well, and between the second drain/source region and the first gate electrode, wherein a bottom of the first isolation region is lower than a bottom of the second drain/source region.

Abstract: A method, computer system, and a computer program product are provided for post-modeling feature evaluation. In one embodiment, at least at least one post model visual output and associated data is obtained that at least includes an individual conditional expectation (ICE) plot and a partial dependence (PDP) plot. Using the associated data and the plots, a Feature Importance (PI) plot is provided. A plurality of features is then determined for each PI, PDP and ICE plots to calculate at least one Interesting Value for each plot. An overall score is also calculated for each plurality of features based on the associated Interesting Values for each PDP, ICE and PI plots. At least one top feature is selected based on said scores. A final plot is then generated at least reflecting the top feature. The final plot combines the PI, PDP and ICE plots together.

Abstract: A technique includes displaying, by a computer using a graphical interface, a map of a geographical area, where the map includes political boundaries. The technique includes displaying, by the computer, graphical images on the map representing a plurality of aspects that are associated with the management of a plurality of projects as corresponding geographical features on the map. The technique includes graphically segregating, by the computer, the plurality of projects on the map using the political boundaries; receiving input, via interaction with the displayed map; and changing, by the computer, in response to the interaction, how a given aspect of the plurality of aspects of a given project of the plurality of projects is represented on the map.

Abstract: An integrated circuit includes an input circuit coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second or a third input signal, and a level shifter circuit coupled to the input circuit and a second voltage supply, and configured to receive a first enable signal, the second or third input signal, and to generate a first signal responsive to the first enable signal, the second or third input signal. The input circuit includes a first set of transistors having a first threshold voltage. The first set of transistors includes a first set of active regions extending in a first direction. The level shifter circuit includes a second set of transistors having a second threshold voltage. The second set of transistors includes a second set of active regions extending in the first direction.

Abstract: A device includes a first buried layer over a substrate, a second buried layer over the first buried layer, a first well over the first buried layer and the second buried layer, a first high voltage well, a second high voltage well and a third high voltage well extending through the first well, wherein the second high voltage well is between the first high voltage well and the third high voltage well, a first drain/source region in the first high voltage well, a first gate electrode over the first well, a second drain/source region in the second high voltage well and a first isolation region in the second high voltage well, and between the second drain/source region and the first gate electrode, wherein a bottom of the first isolation region is lower than a bottom of the second drain/source region.

Abstract: Obtain, at a computing device, a segment of computer code. With a classification module of a machine learning system executing on the computing device, determine a required annotation category for the segment of computer code. With an annotation generation module of the machine learning system executing on the computing device, generate a natural language annotation of the segment of computer code based on the segment of computer code and the required annotation category. Provide the natural language annotation to a user interface for display adjacent the segment of computer code.

Abstract: An ESD protection device protects a circuit from TLPs between a first terminal and a second terminal. The device includes an NPN discharge structure and a PNP triggering device. The first terminal is coupled to the p-doped emitter and the n-doped base of the PNP triggering device and also the n-doped emitter of the NPN discharge structure. The second terminal is coupled to the n-doped collector of the NPN discharge structure. The p-doped collector of the PNP triggering device is coupled to the p-doped base of the NPN discharge structure. A TLP causes base-collector junction breakdown in the PNP triggering device, which results in a current through the PNP triggering device. That current is injected into the base of the NPN discharge structure, which results in a larger discharge current through the NPN discharge structure. The device provides high holding voltage ESD protection device with snapback.

Abstract: An ESD protection device protects a circuit from TLPs between a first terminal and a second terminal. The device includes an NPN discharge structure and a PNP triggering device. The first terminal is coupled to the p-doped emitter and the n-doped base of the PNP triggering device and also the n-doped emitter of the NPN discharge structure. The second terminal is coupled to the n-doped collector of the NPN discharge structure. The p-doped collector of the PNP triggering device is coupled to the p-doped base of the NPN discharge structure. A TLP causes base-collector junction breakdown in the PNP triggering device, which results in a current through the PNP triggering device. That current is injected into the base of the NPN discharge structure, which results in a larger discharge current through the NPN discharge structure. The device provides high holding voltage ESD protection device with snapback.

Abstract: A video capture method includes: controlling an image sensor to capture a plurality of first sensor output frames at a first frame rate during a first period; during the first period, checking if a motion blur condition is met; in response to the motion blur condition being met during the first period, controlling the image sensor to capture a plurality of second sensor output frames at a second frame rate during a second period following the first period, wherein the second frame rate is higher than the first frame rate; and processing consecutive sensor output frames captured by the image sensor during the first period and the second period, to generate a plurality of output frames.

Abstract: An image processing method is provided. The image processing method is applied to an image signal processor. The image processing method includes the stages detailed in the following paragraph. Binned-Bayer raw data and binned-white raw data are received from an image sensor with an RGBW color filter array. The binned-Bayer raw data include information of red, green, and blue channels for a plurality of pixels. The binned-white raw data include luminance information for the pixels. The pixels are rendered based on both the binned-Bayer raw data and the binned-white raw data.

Abstract: A semiconductor device includes an isolation structure in a substrate; and a gate structure over an active region of the substrate. The isolation structure surrounds the active region. The gate structure includes a first section parallel to a second section. The semiconductor device further includes a conductive field plate extending between the first section and the second section and overlapping an edge of the active region. A portion of the conductive field plate extends beyond the edge of the active region, The conductive field plate includes a dielectric layer having a first portion and a second portion, and the first portion is thicker than the second portion. The semiconductor device includes a first well overlapping the edge of the active region. The first well extends underneath the isolation structure. The conductive field plate extends beyond an outer-most edge of the first well.

Abstract: A device for imaging one dimension nanomaterials is provided. The device includes an optical microscope with a liquid immersion objective, a laser device, and a spectrometer. The laser device is configured to provide an incident light beam with a continuous spectrum. The spectrometer is configured to obtain spectral information of the one dimensional nanomaterials.

Abstract: A video capture method includes: controlling an image sensor to capture a plurality of first sensor output frames at a first frame rate during a first period; during the first period, checking if a motion blur condition is met; in response to the motion blur condition being met during the first period, controlling the image sensor to capture a plurality of second sensor output frames at a second frame rate during a second period following the first period, wherein the second frame rate is higher than the first frame rate; and processing consecutive sensor output frames captured by the image sensor during the first period and the second period, to generate a plurality of output frames.

Abstract: An augmented reality-assisted method for performing surgery comprises: disposing a position sensing element at a facial positioning point of a patient before craniotomy to obtain skull space and intracranial space information for defining a coordinate space; obtaining a brain anatomical image for constructing a three-dimensional graphic, the graphic comprising a graphic positioning point and a feature associated with a gyrus feature; defining a relative positional relationship between the graphic and the space, aligning the facial positioning point with the graphic positioning point; using a probe to obtain a spatial position of the gyrus feature after craniotomy, using the gyrus feature as a calibration reference point; generating a displacement and rotation parameter based on a coordinate difference of the feature relative to the reference point; adjusting a position and/or an angle of the graphic on a display according to the parameter, and the display displaying the calibrated three-dimensional graphic.

Abstract: A method of manufacturing a semiconductor device includes forming a gate structure over an active region of a substrate, the gate structure comprising a first section and a second section. The first section and the second section dividing the active region into a first source/drain region between the first section and the second section, and a pair of second source/drain regions arranged on opposite sides of the gate structure. The method further includes forming a conductive field plate over the substrate, the field plate extending between the first section and the second section and overlapping an edge of the active region. The method further includes implanting a first well in the substrate, wherein the first well overlaps the edge of the active region. The method further includes forming an isolation structure in the substrate, wherein the conductive field plate extends over the isolation structure.

Abstract: An ESD protection device protects a circuit from TLPs between a first terminal and a second terminal. The device includes an NPN discharge structure and a PNP triggering device. The first terminal is coupled to the p-doped emitter and the n-doped base of the PNP triggering device and also the n-doped emitter of the NPN discharge structure. The second terminal is coupled to the n-doped collector of the NPN discharge structure. The p-doped collector of the PNP triggering device is coupled to the p-doped base of the NPN discharge structure. A TLP causes base-collector junction breakdown in the PNP triggering device, which results in a current through the PNP triggering device. That current is injected into the base of the NPN discharge structure, which results in a larger discharge current through the NPN discharge structure. The device provides high holding voltage ESD protection device with snapback.

Abstract: The present invention provides a medical image processing method, which comprises following steps of: receiving a three-dimensional model image file and at least one medical record data by a medical image processing device; creating a three-dimensional medical file based on the three-dimensional model image file and the at least one medical record data, wherein the three-dimensional medical file conforms to a digital imaging and communications in medicine standard; transmitting the three-dimensional medical file to a medical picture archiving and communication system; retrieving the three-dimensional medical file from the medical picture archiving and communication system by a three-dimensional medical image browsing device which is a non-workstation computer device loaded with a viewer software; and displaying the three-dimensional medical file.

Abstract: A device includes a first buried layer over a substrate, a second buried layer over the first buried layer, a first well over the first buried layer and the second buried layer, a first high voltage well, a second high voltage well and a third high voltage well extending through the first well, wherein the second high voltage well is between the first high voltage well and the third high voltage well, a first drain/source region in the first high voltage well, a first gate electrode over the first well, a second drain/source region in the second high voltage well and a first isolation region in the second high voltage well, and between the second drain/source region and the first gate electrode, wherein a bottom of the first isolation region is lower than a bottom of the second drain/source region.