Patents by Inventor Jing-Ying CHEN
Jing-Ying CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11935950Abstract: A device includes a first buried layer over a substrate, a second buried layer over the first buried layer, a first well over the first buried layer and the second buried layer, a first high voltage well, a second high voltage well and a third high voltage well extending through the first well, wherein the second high voltage well is between the first high voltage well and the third high voltage well, a first drain/source region in the first high voltage well, a first gate electrode over the first well, a second drain/source region in the second high voltage well and a first isolation region in the second high voltage well, and between the second drain/source region and the first gate electrode, wherein a bottom of the first isolation region is lower than a bottom of the second drain/source region.Type: GrantFiled: August 23, 2021Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Yu Chen, Wan-Hua Huang, Jing-Ying Chen, Kuo-Ming Wu
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Patent number: 11894362Abstract: An ESD protection device protects a circuit from TLPs between a first terminal and a second terminal. The device includes an NPN discharge structure and a PNP triggering device. The first terminal is coupled to the p-doped emitter and the n-doped base of the PNP triggering device and also the n-doped emitter of the NPN discharge structure. The second terminal is coupled to the n-doped collector of the NPN discharge structure. The p-doped collector of the PNP triggering device is coupled to the p-doped base of the NPN discharge structure. A TLP causes base-collector junction breakdown in the PNP triggering device, which results in a current through the PNP triggering device. That current is injected into the base of the NPN discharge structure, which results in a larger discharge current through the NPN discharge structure. The device provides high holding voltage ESD protection device with snapback.Type: GrantFiled: February 5, 2021Date of Patent: February 6, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Jing-Ying Chen
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Publication number: 20230369315Abstract: An ESD protection device protects a circuit from TLPs between a first terminal and a second terminal. The device includes an NPN discharge structure and a PNP triggering device. The first terminal is coupled to the p-doped emitter and the n-doped base of the PNP triggering device and also the n-doped emitter of the NPN discharge structure. The second terminal is coupled to the n-doped collector of the NPN discharge structure. The p-doped collector of the PNP triggering device is coupled to the p-doped base of the NPN discharge structure. A TLP causes base-collector junction breakdown in the PNP triggering device, which results in a current through the PNP triggering device. That current is injected into the base of the NPN discharge structure, which results in a larger discharge current through the NPN discharge structure. The device provides high holding voltage ESD protection device with snapback.Type: ApplicationFiled: July 24, 2023Publication date: November 16, 2023Inventor: Jing-Ying Chen
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Publication number: 20230107025Abstract: A semiconductor device includes an isolation structure in a substrate; and a gate structure over an active region of the substrate. The isolation structure surrounds the active region. The gate structure includes a first section parallel to a second section. The semiconductor device further includes a conductive field plate extending between the first section and the second section and overlapping an edge of the active region. A portion of the conductive field plate extends beyond the edge of the active region, The conductive field plate includes a dielectric layer having a first portion and a second portion, and the first portion is thicker than the second portion. The semiconductor device includes a first well overlapping the edge of the active region. The first well extends underneath the isolation structure. The conductive field plate extends beyond an outer-most edge of the first well.Type: ApplicationFiled: November 29, 2022Publication date: April 6, 2023Inventors: Po-Yu CHEN, Wan-Hua HUANG, Jing-Ying CHEN
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Patent number: 11527624Abstract: A method of manufacturing a semiconductor device includes forming a gate structure over an active region of a substrate, the gate structure comprising a first section and a second section. The first section and the second section dividing the active region into a first source/drain region between the first section and the second section, and a pair of second source/drain regions arranged on opposite sides of the gate structure. The method further includes forming a conductive field plate over the substrate, the field plate extending between the first section and the second section and overlapping an edge of the active region. The method further includes implanting a first well in the substrate, wherein the first well overlaps the edge of the active region. The method further includes forming an isolation structure in the substrate, wherein the conductive field plate extends over the isolation structure.Type: GrantFiled: January 28, 2020Date of Patent: December 13, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Yu Chen, Wan-Hua Huang, Jing-Ying Chen
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Publication number: 20220254772Abstract: An ESD protection device protects a circuit from TLPs between a first terminal and a second terminal. The device includes an NPN discharge structure and a PNP triggering device. The first terminal is coupled to the p-doped emitter and the n-doped base of the PNP triggering device and also the n-doped emitter of the NPN discharge structure. The second terminal is coupled to the n-doped collector of the NPN discharge structure. The p-doped collector of the PNP triggering device is coupled to the p-doped base of the NPN discharge structure. A TLP causes base-collector junction breakdown in the PNP triggering device, which results in a current through the PNP triggering device. That current is injected into the base of the NPN discharge structure, which results in a larger discharge current through the NPN discharge structure. The device provides high holding voltage ESD protection device with snapback.Type: ApplicationFiled: February 5, 2021Publication date: August 11, 2022Inventor: Jing-Ying Chen
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Publication number: 20210384349Abstract: A device includes a first buried layer over a substrate, a second buried layer over the first buried layer, a first well over the first buried layer and the second buried layer, a first high voltage well, a second high voltage well and a third high voltage well extending through the first well, wherein the second high voltage well is between the first high voltage well and the third high voltage well, a first drain/source region in the first high voltage well, a first gate electrode over the first well, a second drain/source region in the second high voltage well and a first isolation region in the second high voltage well, and between the second drain/source region and the first gate electrode, wherein a bottom of the first isolation region is lower than a bottom of the second drain/source region.Type: ApplicationFiled: August 23, 2021Publication date: December 9, 2021Inventors: Po-Yu Chen, Wan-Hua Huang, Jing-Ying Chen, Kuo-Ming Wu
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Patent number: 11107916Abstract: A device includes a first buried layer over a substrate, a second buried layer over the first buried layer, a first well over the first buried layer and the second buried layer, a first high voltage well, a second high voltage well and a third high voltage well extending through the first well, wherein the second high voltage well is between the first high voltage well and the third high voltage well, a first drain/source region in the first high voltage well, a first gate electrode over the first well, a second drain/source region in the second high voltage well and a first isolation region in the second high voltage well, and between the second drain/source region and the first gate electrode, wherein a bottom of the first isolation region is lower than a bottom of the second drain/source region.Type: GrantFiled: April 3, 2019Date of Patent: August 31, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Yu Chen, Wan-Hua Huang, Jing-Ying Chen, Kuo-Ming Wu
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Publication number: 20200168713Abstract: A method of manufacturing a semiconductor device includes forming a gate structure over an active region of a substrate, the gate structure comprising a first section and a second section. The first section and the second section dividing the active region into a first source/drain region between the first section and the second section, and a pair of second source/drain regions arranged on opposite sides of the gate structure. The method further includes forming a conductive field plate over the substrate, the field plate extending between the first section and the second section and overlapping an edge of the active region. The method further includes implanting a first well in the substrate, wherein the first well overlaps the edge of the active region. The method further includes forming an isolation structure in the substrate, wherein the conductive field plate extends over the isolation structure.Type: ApplicationFiled: January 28, 2020Publication date: May 28, 2020Inventors: Po-Yu CHEN, Wan-Hua HUANG, Jing-Ying CHEN
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Patent number: 10553687Abstract: A semiconductor device includes a substrate having an active region, a drain region in the active region, a source region in the active region, a gate structure, and a conductive field plate. The gate structure extends in a first direction over the active region. The gate structure is arranged between the drain region and the source region in a second direction transverse to the first direction. The conductive field plate extends in the second direction over an edge of the active region.Type: GrantFiled: October 11, 2013Date of Patent: February 4, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Yu Chen, Wan-Hua Huang, Jing-Ying Chen
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Publication number: 20190229214Abstract: A device includes a first buried layer over a substrate, a second buried layer over the first buried layer, a first well over the first buried layer and the second buried layer, a first high voltage well, a second high voltage well and a third high voltage well extending through the first well, wherein the second high voltage well is between the first high voltage well and the third high voltage well, a first drain/source region in the first high voltage well, a first gate electrode over the first well, a second drain/source region in the second high voltage well and a first isolation region in the second high voltage well, and between the second drain/source region and the first gate electrode, wherein a bottom of the first isolation region is lower than a bottom of the second drain/source region.Type: ApplicationFiled: April 3, 2019Publication date: July 25, 2019Inventors: Po-Yu Chen, Wan-Hua Huang, Jing-Ying Chen, Kuo-Ming Wu
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Patent number: 10290714Abstract: In some embodiments, a BJT structure includes a base region, an emitter region formed in the base region and including an emitter doping region, a collector region including a collector doping region, an insulating structure and a field plate. The base region forms a junction with the collector region between the emitter and collector doping regions. The field plate is formed over an insulating structure over the junction. A first distance between the corresponding emitter and collector doping regions to the junction is shorter than a second distance in another BJT structure without the field plate corresponding to the first distance. The first distance causes a breakdown of the junction corresponding to a first breakdown voltage value between the emitter and collector doping regions being substantially the same or greater than a second breakdown voltage value of the other BJT structure corresponding to the first breakdown voltage value.Type: GrantFiled: May 31, 2016Date of Patent: May 14, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Jing-Ying Chen, Yu-Chang Jong, Shui-Ming Cheng
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Patent number: 10269959Abstract: A device comprises a buried layer over a substrate, a first well over the buried layer, a first high voltage region and a second high voltage region extending through the first well, a first drain/source region in the first high voltage region, a first gate electrode over the first well, a first spacer on a first side of the first gate electrode, wherein the first spacer is between the first drain/source region and the first gate electrode, a second spacer on a second side of the first gate electrode, a second drain/source region in the second high voltage region and a first isolation region in the second high voltage region and between the second drain/source region and the first gate electrode.Type: GrantFiled: October 10, 2017Date of Patent: April 23, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Yu Chen, Wan-Hua Huang, Jing-Ying Chen, Kuo-Ming Wu
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Publication number: 20180033888Abstract: A device comprises a buried layer over a substrate, a first well over the buried layer, a first high voltage region and a second high voltage region extending through the first well, a first drain/source region in the first high voltage region, a first gate electrode over the first well, a first spacer on a first side of the first gate electrode, wherein the first spacer is between the first drain/source region and the first gate electrode, a second spacer on a second side of the first gate electrode, a second drain/source region in the second high voltage region and a first isolation region in the second high voltage region and between the second drain/source region and the first gate electrode.Type: ApplicationFiled: October 10, 2017Publication date: February 1, 2018Inventors: Po-Yu Chen, Wan-Hua Huang, Jing-Ying Chen, Kuo-Ming Wu
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Publication number: 20170345902Abstract: In some embodiments, a BJT structure includes a base region, an emitter region formed in the base region and including an emitter doping region, a collector region including a collector doping region, an insulating structure and a field plate. The base region forms a junction with the collector region between the emitter and collector doping regions. The field plate is formed over an insulating structure over the junction. A first distance between the corresponding emitter and collector doping regions to the junction is shorter than a second distance in another BJT structure without the field plate corresponding to the first distance. The first distance causes a breakdown of the junction corresponding to a first breakdown voltage value between the emitter and collector doping regions being substantially the same or greater than a second breakdown voltage value of the other BJT structure corresponding to the first breakdown voltage value.Type: ApplicationFiled: May 31, 2016Publication date: November 30, 2017Inventors: JING-YING CHEN, YU-CHANG JONG, SHUI-MING CHENG
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Patent number: 9799766Abstract: A high voltage transistor structure comprises a first double diffused region and a second double diffused region formed in a first well of a substrate, wherein the first and second double diffused regions are of the same conductivity as the substrate, a first drain/source region formed in the first double diffused region, a first gate electrode formed over the first well and a second drain/source region formed in the second double diffused region. The high voltage transistor structure further comprises a first spacer formed on a first side of the first gate electrode, wherein the first spacer is between the first drain/source region and the first gate electrode, a second spacer formed on a second side of the first gate electrode and a first oxide protection layer formed between the second drain/source region and the second spacer.Type: GrantFiled: February 20, 2013Date of Patent: October 24, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Yu Chen, Wan-Hua Huang, Jing-Ying Chen, Kuo-Ming Wu
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Patent number: 9761494Abstract: A semiconductor structure includes a gate structure disposed on a substrate. At least one lightly doped region adjoins the gate structure in the substrate. The at least one lightly doped region has a first conductivity type. A source feature and a drain feature are on opposite sides of the gate structure in the substrate. The source feature and the drain feature have the first conductivity type. The source feature is in the at least one lightly doped region. A bulk pick-up region adjoins the source feature in the at least one lightly doped region. The bulk pick-up region has a second conductivity type.Type: GrantFiled: May 7, 2012Date of Patent: September 12, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Yu Chen, Wan-Hua Huang, Jing-Ying Chen, Kuo-Ming Wu
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Publication number: 20150102427Abstract: A semiconductor device includes a substrate having an active region, a drain region in the active region, a source region in the active region, a gate structure, and a conductive field plate. The gate structure extends in a first direction over the active region. The gate structure is arranged between the drain region and the source region in a second direction transverse to the first direction. The conductive field plate extends in the second direction over an edge of the active region.Type: ApplicationFiled: October 11, 2013Publication date: April 16, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Yu CHEN, Wan-Hua HUANG, Jing-Ying CHEN
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Publication number: 20130292781Abstract: A semiconductor structure includes a gate structure disposed on a substrate. At least one lightly doped region adjoins the gate structure in the substrate. The at least one lightly doped region has a first conductivity type. A source feature and a drain feature are on opposite sides of the gate structure in the substrate. The source feature and the drain feature have the first conductivity type. The source feature is in the at least one lightly doped region. A buck pick-up region adjoins the source feature in the at least one lightly doped region. The buck pick-up region has a second conductivity type.Type: ApplicationFiled: May 7, 2012Publication date: November 7, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Yu CHEN, Wan-Hua HUANG, Jing-Ying CHEN, Kuo-Ming WU