Abstract: A frequency synchronization method includes: receiving, by a slave clock, a first pulse signal and a second pulse signal; determining, by the slave clock based on a first phase difference, a second phase difference, a first delay, and a second delay, that a frequency offset of the slave clock relative to the master clock is equal to a first frequency offset, where the first phase difference is a difference between a phase of a third pulse signal generated by the slave clock and a phase of the first pulse signal received by the slave clock, and the second phase difference is a difference between a phase of a fourth pulse signal generated by the slave clock and a phase of the second pulse signal received by the slave clock; and calibrating, by the slave clock, frequency of the slave clock based on the first frequency offset.

Abstract: A method for synchronizing a network device includes: receiving, by the network device, a first SSM and a second SSM, where the first SSM carries a first SSM code for indicating a quality level of a first clock source and a first eSSM code for indicating the quality level of the first clock source, and the second SSM carries a second SSM code for indicating a quality level of a second clock source and a second eSSM code for indicating the quality level of the second clock source. When a value of the first SSM code is less than a value of the second SSM code, the network device calibrates a frequency of the network device based on a timing signal of the first clock source.

Abstract: A network device synchronization method is provided. In various embodiments, a first SSM and a second SSM are received. The first SSM carries a first SSM code indicating a quality level of a first clock source and a first eSSM code indicating the quality level of the first clock source, the second SSM carries a second SSM code indicating a quality level of a second clock source. The second SSM lacks an eSSM code indicating the quality level of the second clock source, and a value of the first SSM code is equal to a value of the second SSM code. When a value of the first eSSM code is less than 0xFF, calibrating a frequency of the network device based on a timing signal of the first clock source.

Abstract: A current holding circuit for a bidirectional triode thyristor (TRIAC) dimmer and a linear dimming driving circuit are provided. The current holding circuit for a TRIAC dimmer is a resistance and capacitance (RC) circuit including a first resistor and a first capacitor connected in series. The RC circuit is connected in parallel with any one of rectifying diodes of a rectifying bridge in the linear dimming driving circuit. The linear dimming driving circuit includes an overcurrent protecting circuit, a rectifying bridge including four rectifying diodes connected, the RC circuit, a surge suppressing circuit configured to absorb a high surge voltage of an input voltage, a filtering circuit, a linear constant-current circuit, and a flicker eliminating circuit configured to eliminate flicker caused by an asymmetrical current of a light emitting diode (LED) load due to the RC circuit.

Abstract: A frequency synchronization method includes: receiving, by a slave clock, a first pulse signal and a second pulse signal; determining, by the slave clock based on a first phase difference, a second phase difference, a first delay, and a second delay, that a frequency offset of the slave clock relative to the master clock is equal to a first frequency offset, where the first phase difference is a difference between a phase of a third pulse signal generated by the slave clock and a phase of the first pulse signal received by the slave clock, and the second phase difference is a difference between a phase of a fourth pulse signal generated by the slave clock and a phase of the second pulse signal received by the slave clock; and calibrating, by the slave clock, frequency of the slave clock based on the first frequency offset.

Abstract: A current holding circuit for a bidirectional triode thyristor (TRIAC) dimmer and a linear dimming driving circuit are provided. The current holding circuit for a TRIAC dimmer is a resistance and capacitance (RC) circuit including a first resistor and a first capacitor connected in series. The RC circuit is connected in parallel with any one of rectifying diodes of a rectifying bridge in the linear dimming driving circuit. The linear dimming driving circuit includes an overcurrent protecting circuit, a rectifying bridge including four rectifying diodes connected, the RC circuit, a surge suppressing circuit configured to absorb a high surge voltage of an input voltage, a filtering circuit, a linear constant-current circuit, and a flicker eliminating circuit configured to eliminate flicker caused by an asymmetrical current of a light emitting diode (LED) load due to the RC circuit.