Patents by Inventor Jingfeng Bi
Jingfeng Bi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240304757Abstract: Disclosed is a vertical structure deep ultraviolet LED, a manufacturing method thereof and an epitaxial structure. The manufacturing method comprises: forming an epitaxial structure on a sapphire substrate, the epitaxial structure having a first surface and a second surface connected with the sapphire substrate; dividing the epitaxial structure into epitaxial units arranged in an array, a portion of the sapphire substrate being exposed between adjacent epitaxial units; forming an adhesive layer on a portion, which is exposed between adjacent epitaxial units, of the sapphire substrate; bonding a second substrate above the first surface of the epitaxial structure; performing laser lift-off on the sapphire substrate; and removing the adhesive layer. By dividing the epitaxial structure into epitaxial units arranged in an array, the manufacturing method alleviates the problem of serious damage to the epitaxial structure caused by strong impact generated at the moment of high energy density laser lift-off.Type: ApplicationFiled: March 1, 2022Publication date: September 12, 2024Inventors: Weihong Fan, Jingfeng Bi, Maofang Guo, Shitao Li, Jinchao Zhao, Shiman Shi, Quanxin Jin
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Publication number: 20240204134Abstract: A semiconductor light emitting element and a manufacture method thereof are provided. The semiconductor light emitting element includes: a substrate, an n-type semiconductor layer, a quantum well layer and a p-type semiconductor layer being arranged sequentially from bottom to top, and further includes a surface plasmon excition layer being arranged on the p-type semiconductor layer and a surface plasmon excited layer being arranged between the quantum well layer and the p-type semiconductor layer, or the surface plasmon excitation layer being arranged between the p-type semiconductor layer and the surface plasmon excitation layer, or the surface plasmon excitation layers being arranged respectively between the quantum well layer and the p-type semiconductor layer and between the p-type semiconductor layer and the surface plasmon excitation layer.Type: ApplicationFiled: March 1, 2022Publication date: June 20, 2024Inventors: Jinjian Zheng, Moran Gao, Jingfeng Bi, Weihong Fan, Senlin Li, Jiaming Zeng, Yuanjie Wu, Chengjun Zhang
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Publication number: 20240204133Abstract: A semiconductor light emitting element is provided and includes: a substrate, an n-type semiconductor layer, a doped quantum well layer, a control layer for suppressing light attenuation with age and a p-type semiconductor layer from bottom to top. The control layer for suppressing light attenuation with age sequentially includes an undoped quantum well layer having at least one undoped barrier layer, a first control layer for suppressing light attenuation and/or a second control layer for suppressing light attenuation from bottom to top. The present disclosure reduces probability of Si of the doped quantum well layer and Mg of the p-type semiconductor layer diffusing and coming into contact with each other during long-term aging process, thereby suppressing light attenuation with age of the semiconductor light emitting element. A light attenuation of 1000 hours is reduced from 30% or higher (even 50% or higher) to within 10%.Type: ApplicationFiled: March 1, 2022Publication date: June 20, 2024Inventors: Jinjian Zheng, Moran Gao, Jingfeng Bi, Weihong Fan, Jiaming Zeng, Chengjun Zhang
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Patent number: 11876154Abstract: A light-emitting diode (LED) device includes a first epitaxial layered structure having an upper surface having different first and second regions, a second epitaxial layered structure spaced-apart disposed on the first epitaxial layered structure, a light conversion layer formed on the first region, a bonding unit disposed on the light conversion layer, the bonding unit and the light conversion layer interconnecting the first and second epitaxial layered structures, and an electrically conductive structure formed on the second region and electrically connects the first and second epitaxial layered structures. A method for manufacturing the LED device is also disclosed.Type: GrantFiled: February 20, 2020Date of Patent: January 16, 2024Assignee: Xiamen San'An Optoelectronics Co., Ltd.Inventors: Mingyang Li, Guanzhou Liu, Jingfeng Bi, Senlin Li, Minghui Song, Wenjun Chen
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Publication number: 20230343893Abstract: The present disclosure relates to an epitaxial structure for light emitting diode and a light emitting diode. The epitaxial structure for light emitting diode comprises a substrate, a buffer layer, a distributed Bragg reflector, and a semiconductor stack in an order from bottom to top. The distributed Bragg reflector includes a low refractive-index film and a high refractive-index film above the low refractive-index film, and a thickness of the high refractive-index film is thinner than an optical thickness of the high refractive-index film. The present disclosure can reduce light absorption of the distributed Bragg reflector and improve reflectivity and light output intensity of the distributed Bragg reflector by adjusting the thickness of the high refractive-index film.Type: ApplicationFiled: March 1, 2022Publication date: October 26, 2023Inventors: Senlin Li, Yahong Wang, Meijia Yang, Jingfeng Bi, Weihong Fan
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Patent number: 11043609Abstract: A light emitting diode includes an n-type confinement layer, a quantum well active layer formed on the n-type confinement layer, a p-type confinement layer formed on the quantum well active layer, a gallium phosphide-based quantum dot structure formed in the p-type confinement layer, and a GaP-based current spreading layer formed on the GaP-based quantum dot structure. A method of manufacturing the light emitting diode is also provided.Type: GrantFiled: September 26, 2019Date of Patent: June 22, 2021Assignee: XIAMEN SAN'AN OPTOELECTRONICS CO., LTD.Inventors: Senlin Li, Jingfeng Bi, Chun-Kai Huang, Jin Wang, Chih-Hung Hsiao, Chun-I Wu, Du-Xiang Wang
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Patent number: 11011674Abstract: A multi-layered tunnel junction structure adapted to be disposed between two light emitting structures includes an n-type doped insulation layer, as well as an n-type heavily doped layer, a metal atom layer, a p-type heavily doped layer, and a p-type doped insulation layer which are disposed on the n-type doped insulation layer in such sequential order. A light emitting device having the multi-layered tunnel junction structure and a production method of such light emitting device are also disclosed.Type: GrantFiled: December 12, 2019Date of Patent: May 18, 2021Assignee: Xiamen San'an Optoelectronics Co., Ltd.Inventors: Jingfeng Bi, Chaoyu Wu, Duxiang Wang, Senlin Li, Chun-Yi Wu, Shih-Yi Lien
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Publication number: 20210013354Abstract: A solar cell includes a cell chip unit, and an optical unit. The optical unit includes a first optical layer, a second optical layer and a third optical layer that are sequentially disposed on the cell chip unit in such order. Each of the first optical layer and the third optical layer has a refractive index greater than that of the second optical layer.Type: ApplicationFiled: September 29, 2020Publication date: January 14, 2021Inventors: Guanzhou LIU, Mingyang LI, Senlin LI, Minghui SONG, Jingfeng BI, Wenjun CHEN
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Publication number: 20200194634Abstract: A light-emitting diode (LED) device includes a first epitaxial layered structure having an upper surface having different first and second regions, a second epitaxial layered structure spaced-apart disposed on the first epitaxial layered structure, a light conversion layer formed on the first region, a bonding unit disposed on the light conversion layer, the bonding unit and the light conversion layer interconnecting the first and second epitaxial layered structures, and an electrically conductive structure formed on the second region and electrically connects the first and second epitaxial layered structures. A method for manufacturing the LED device is also disclosed.Type: ApplicationFiled: February 20, 2020Publication date: June 18, 2020Inventors: Mingyang LI, Guanzhou LIU, Jingfeng BI, Senlin LI, Minghui SONG, Wenjun CHEN
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Publication number: 20200119224Abstract: A multi-layered tunnel junction structure adapted to be disposed between two light emitting structures includes an n-type doped insulation layer, as well as an n-type heavily doped layer, a metal atom layer, a p-type heavily doped layer, and a p-type doped insulation layer which are disposed on the n-type doped insulation layer in such sequential order. A light emitting device having the multi-layered tunnel junction structure and a production method of such light emitting device are also disclosed.Type: ApplicationFiled: December 12, 2019Publication date: April 16, 2020Inventors: JINGFENG BI, CHAOYU WU, DUXIANG WANG, SENLIN LI, CHUN-YI WU, SHIH-YI LIEN
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Publication number: 20200020826Abstract: A light emitting diode includes an n-type confinement layer, a quantum well active layer formed on the n-type confinement layer, a p-type confinement layer formed on the quantum well active layer, a gallium phosphide-based quantum dot structure formed in the p-type confinement layer, and a GaP-based current spreading layer formed on the GaP-based quantum dot structure. A method of manufacturing the light emitting diode is also provided.Type: ApplicationFiled: September 26, 2019Publication date: January 16, 2020Inventors: SENLIN LI, JINGFENG BI, CHUN KAI HUANG, JIN WANG, SHIH-YI LIEN, CHUN-YI WU, DUXIANG WANG
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Publication number: 20170338361Abstract: A flip-chip multi junction solar cell chip integrated with a bypass diode includes from up to bottom: a glass cover; a transparent bonding layer; a front electrode; an n/p photoelectric conversion layer; a p/n tunnel junction; a structure layer of the n/p bypass diode; a first backside electrode; a second backside electrode. The solar cell chip also includes at least a through hole extending through the n/p photoelectric conversion layer, the p/n tunnel junction and the structure layer of the n/p bypass diode. An ultra-thin substrate-less cell can therefore be provided without occupying effective light receiving areas, greatly improving cell heat dissipation. With a light weight, the chip can also have advantages in space power application.Type: ApplicationFiled: August 5, 2017Publication date: November 23, 2017Applicant: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Weiping XIONG, Jingfeng BI, Wenjun CHEN, Guanzhou LIU, Meijia YANG, Mingyang LI, Chaoyu WU, Duxiang WANG
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Publication number: 20170069782Abstract: A method of fabricating a four-junction solar cell includes: forming a first epitaxial structure comprising first and second subcells and a cover layer over a first substrate through a forward epitaxial growth, and forming a second epitaxial structure comprising third and fourth subcells over the second substrate; forming a groove and a metal bonding layer; forming a groove on the cover layer surface of the first epitaxial structure and the substrate back surface of the second epitaxial structure, and depositing a metal bonding layer in the groove; and bonding the first epitaxial structure and the second epitaxial structure; bonding the cover layer surface of the first epitaxial structure and the substrate back surface of the second epitaxial structure, ensuring that the metal bonding layers are aligned to each other to realize dual bonding between the metal bonding layers and between the semiconductors through high temperature and high pressure treatment.Type: ApplicationFiled: November 21, 2016Publication date: March 9, 2017Applicant: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Minghui SONG, Guijiang LIN, Wenjun CHEN, Jingfeng BI, Guanzhou LIU, Meijia YANG, Mingyang LI
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Patent number: 9437769Abstract: A four-junction quaternary compound solar cell and a method thereof are provided. Forming a first subcell (100) with a first band gap, a lattice constant matching with the substrate on an InP grown substrate, forming a second subcell (200) with a second band gap bigger than the first band gap, a lattice constant matching with the substrate on the first subcell, forming a graded buffer layer (600) with a third band gap bigger than the second band gap on the second subcell, forming a third subcell (300) with a fourth band gap bigger than the third band gap, a lattice constant smaller than the substrate on the graded buffer layer, forming a fourth subcell (400) with a fifth band gap bigger than the fourth band gap, a lattice constant matching with the third subcell on the third subcell, and then forming the required four-junction solar cell then by succeeding process including removing the grown substrate, bonding a support substrate, forming electrodes, evaporating an anti-reflect film and so on.Type: GrantFiled: December 21, 2012Date of Patent: September 6, 2016Assignee: Xiamen Sanan Optoelectronics Technology Co., Ltd.Inventors: Jingfeng Bi, Guijiang Lin, Jianqing Liu, Weiping Xiong, Minghui Song, Liangjun Wang, Jie Ding, Zhidong Lin
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Patent number: 9318643Abstract: A fabrication method for an inverted solar cell includes: (1) providing a growth substrate; (2) depositing a SiO2 mask layer over the surface of the growth substrate to form a patterned substrate; (3) forming a sacrificial layer with epitaxial growth over the patterned substrate, wherein the sacrificial layer encompasses the entire SiO2 mask pattern; (4) forming a buffer layer over the sacrificial layer via epitaxial growth; (5) forming a semiconductor material layer sequence of the inverted solar cell over the buffer layer with epitaxial growth; (6) bonding the semiconductor material layer sequence of the inverted solar cell with a supporting substrate; (7) selectively etching the SiO2 mask layer by wet etching; and (8) selectively etching the sacrificial layer by wet etching to lift off the growth substrate.Type: GrantFiled: January 4, 2014Date of Patent: April 19, 2016Assignee: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Minghui Song, Guijiang Lin, Zhihao Wu, Liangjun Wang, Jianqing Liu, Jingfeng Bi, Weiping Xiong, Zhidong Lin
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Publication number: 20150068581Abstract: A fabrication method for high-efficiency multi junction solar cells, including: providing a Ge substrate for semiconductor epitaxial growth; growing an emitter region over the Ge substrate (as the base) to form a first subcell with a first band gap; forming a second subcell with a second band gap larger than the first band gap and lattice matched with the first subcell over the first subcell via MBE; forming a third subcell with a third band gap larger than the second band gap and lattice matched with the first and second subcells over the second subcell via MOCVD; and forming a fourth subcell with a fourth band gap larger than the third band gap and lattice matched with the first, second and third subcells over the third subcell via MOCVD.Type: ApplicationFiled: November 13, 2014Publication date: March 12, 2015Applicant: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: JINGFENG BI, GUIJIANG LIN, JIANQING LIU, JIE DING
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Publication number: 20140373907Abstract: A four-junction quaternary compound solar cell and a method thereof are provided.Type: ApplicationFiled: December 21, 2012Publication date: December 25, 2014Applicant: Xiamen Sanan Optoelectronics Technology Co., Ltd.Inventors: Jingfeng Bi, Guijiang Lin, Jianqing Liu, Weiping Xiong, Minghui Song, Liangjun Wang, Jie Ding, Zhidong Lin
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Publication number: 20140120656Abstract: A fabrication method for an inverted solar cell includes: (1) providing a growth substrate; (2) depositing a SiO2 mask layer over the surface of the growth substrate to form a patterned substrate; (3) forming a sacrificial layer with epitaxial growth over the patterned substrate, wherein the sacrificial layer encompasses the entire SiO2 mask pattern; (4) forming a buffer layer over the sacrificial layer via epitaxial growth; (5) forming a semiconductor material layer sequence of the inverted solar cell over the buffer layer with epitaxial growth; (6) bonding the semiconductor material layer sequence of the inverted solar cell with a supporting substrate; (7) selectively etching the SiO2 mask layer by wet etching; and (8) selectively etching the sacrificial layer by wet etching to lift off the growth substrate.Type: ApplicationFiled: January 4, 2014Publication date: May 1, 2014Applicant: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: MINGHUI SONG, GUIJIANG LIN, ZHIHAO WU, LIANGJUN WANG, JIANQING LIU, JINGFENG BI, WEIPING XIONG, ZHIDONG LIN
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Publication number: 20140090700Abstract: A high-concentration multi-junction solar cell and method for fabricating same is provided. The high-concentration multi-junction solar cell comprises a top cell, an intermediate cell, a bottom cell and two tunneling junctions connecting the top cell and intermediate cell and the intermediate cell and bottom cell. The emitter layers of the top and intermediate cells both employ the graded doping concentrations and have high open circuit voltage and short circuit current. The top cell emitter layer is over several hundred nanometers thicker than that of the traditional multi-junction cell so as to decrease the whole series resistance of the multi-junction cell, improve the fill factor, and gain higher photoelectric conversion efficiency.Type: ApplicationFiled: May 7, 2012Publication date: April 3, 2014Applicant: Xiamen Sanan Optoelectroics Technology Co., Ltd.Inventors: Minghui Song, Guijiang Lin, Zhihao Wu, Liangjun Wang, Jianqing Liu, Jingfeng Bi, Weiping Xiong, Zhidong Lin