Abstract: A control system method and apparatus that minimizes the difference between multiple state-derived signals, with application to frequency synthesis, is described. Existing Alias-Locked Loops (ALLs) use digital samplers in the feedback path to achieve a wide frequency lock range for high speed frequency synthesis, at the cost of one additional reference clock, compared to a Phase-Locked Loop (PLL). We propose the differential alias-locked loop (D-ALL) circuit architecture which uses only one reference clock input. In this D-ALL synthesizer architecture, two frequencies are derived from the voltage-controlled oscillator (VCO) output and are compared as the two inputs to the phase frequency detector (PFD). In contrast, a PLL or an ALL has a reference clock as one PFD input and a frequency derived from the VCO output as the other PFD input.