Patents by Inventor Jingjing Geng
Jingjing Geng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11990506Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack on the substrate, a plurality of channel structures each extending vertically through the memory stack, and one or more isolation structures. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. An outmost one of the conductive layers toward the substrate is a source select gate line (SSG). Each isolation structure surrounds at least one of the channel structures in a plan view to separate the SSG and the at least one channel structure.Type: GrantFiled: October 29, 2020Date of Patent: May 21, 2024Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Jiajia Wu, Jingjing Geng, Yang Zhou, Zhen Guo, Meng Xiao, Hui Zhang
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Patent number: 11985824Abstract: Three-dimensional (3D) memory devices and methods for forming the 3D memory devices are provided. In one example, a 3D memory device includes a substrate and a memory stack including interleaved conductive layers and dielectric layers on the substrate. The memory stack includes a core structure and a staircase structure. The staircase structure is on one side of the memory stack. The 3D memory device also includes a dummy channel structure extending vertically through the staircase structure. The dummy channel structure includes a plurality of sections along a vertical side of the dummy channel structure. The plurality of sections respectively interface with the interleaved conductive layers in the staircase structure. At least one of the plurality of sections includes a non-flat surface at an interface between the at least one of the plurality of sections and a corresponding conductive layer.Type: GrantFiled: October 29, 2020Date of Patent: May 14, 2024Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Jianzhong Wu, Jingjing Geng
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Patent number: 11950418Abstract: Embodiments of a three-dimensional (3D) memory device and fabrication methods thereof are disclosed. In an example, a method for forming a 3D memory device includes the following operations. A dielectric stack is formed to have interleaved sacrificial layers and dielectric layers. A stair is formed in the dielectric stack. The stair includes one or more sacrificial layers of the sacrificial layers and one or more dielectric layers of the dielectric layers. The stair exposes one of the sacrificial layers on a top surface and the one or more sacrificial layers on a side surface. An insulating portion is formed to cover the side surface of the stair to cover the one or more sacrificial layers. A sacrificial portion is formed to cover the top surface of the stair. The sacrificial portion is in contact with the one of sacrificial layers. The one or more sacrificial layers and the sacrificial portion are replaced with one or more conductor layers.Type: GrantFiled: March 30, 2021Date of Patent: April 2, 2024Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Xinxin Liu, Jingjing Geng, Zhu Yang, Chen Zuo, Xiangning Wang
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Patent number: 11937427Abstract: In certain aspects, a first opening extending vertically through a first dielectric deck including a first plurality of interleaved sacrificial layers and dielectric layers above a substrate is formed. A high-k dielectric layer and a channel sacrificial layer free of polysilicon are subsequently formed along a sidewall of the first opening. A second opening extending vertically through a second dielectric deck including a second plurality of interleaved sacrificial layers and dielectric layers on the first dielectric deck is formed to expose the channel sacrificial layer in the first opening. The channel sacrificial layer is removed in the first opening. A memory film and a semiconductor channel are subsequently formed over the high-k dielectric layer along sidewalls of the first and second openings.Type: GrantFiled: May 24, 2021Date of Patent: March 19, 2024Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Shuangshuang Peng, Jingjing Geng, Jiajia Wu, Tuo Li
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Patent number: 11800707Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers above the substrate, and a channel structure extending vertically through the memory stack. The channel structure includes a high dielectric constant (high-k) dielectric layer disposed continuously along a sidewall of the channel structure, a memory film over the high-k dielectric layer along the sidewall of the channel structure, and a semiconductor channel over the memory film along the sidewall of the channel structure.Type: GrantFiled: May 22, 2020Date of Patent: October 24, 2023Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Shuangshuang Peng, Jingjing Geng, Jiajia Wu, Tuo Li
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Publication number: 20230301106Abstract: Embodiments of three-dimensional (3D) memory devices are disclosed. In an example, a 3D memory device includes a semiconductor layer, a memory stack over the semiconductor layer, first channel structures each extending vertically through the memory stack in an edge region, and an isolation structure. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. At least one of conductive layers toward the semiconductor layer is a source select gate line (SSG). The isolation structure extends vertically through the SSG and into the semiconductor layer. The memory stack includes a core array region, a staircase region, and the edge region being laterally between the core array region and the staircase region. At least one of the first channel structures extends through the isolation structure and is separated from the SSG through the isolation structure.Type: ApplicationFiled: May 25, 2023Publication date: September 21, 2023Inventors: Zhen Guo, Jingjing Geng, Bin Yuan, Jiajia Wu, Xiangning Wang, Zhu Yang, Chen Zuo
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Patent number: 11711921Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack on the substrate, a plurality of channel structures each extending vertically through the memory stack, an isolation structure, and an alignment mark. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. An outmost one of the conductive layers toward the substrate is a source select gate line (SSG). The isolation structure extends vertically into the substrate and surrounds at least one of the channel structures in a plan view to separate the SSG and the at least one channel structure. The alignment mark extends vertically into the substrate and is coplanar with the isolation structure.Type: GrantFiled: October 29, 2020Date of Patent: July 25, 2023Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Zhen Guo, Jingjing Geng, Bin Yuan, Jiajia Wu, Xiangning Wang, Zhu Yang, Chen Zuo
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Publication number: 20230095343Abstract: Embodiments of a three-dimensional (3D) memory device and fabrication methods thereof are disclosed. In an example, a 3D memory device includes a memory stack having a plurality of stairs. Each stair may include interleaved one or more conductor layers and one or more dielectric layers. Each of the stairs includes one of the conductor layers on a top surface of the stair, the one of the conductor layers having (i) a bottom portion in contact with one of the dielectric layers, and (ii) a top portion exposed by the memory stack and in contact with the bottom portion. A lateral dimension of the top portion may be less than a lateral dimension of the bottom portion. An end of the top portion that may be facing away from the memory stack laterally exceeds the bottom portion by a distance.Type: ApplicationFiled: December 8, 2022Publication date: March 30, 2023Inventors: Xinxin Liu, Jingjing Geng, Zhu Yang, Chen Zuo, Xiangning Wang
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Patent number: 11552097Abstract: Embodiments of a three-dimensional (3D) memory device and fabrication methods thereof are disclosed. In an example, a 3D memory device includes a memory stack having a plurality of stairs. Each stair may include interleaved one or more conductor layers and one or more dielectric layers. Each of the stairs includes one of the conductor layers on a top surface of the stair, the one of the conductor layers having (i) a bottom portion in contact with one of the dielectric layers, and (ii) a top portion exposed by the memory stack and in contact with the bottom portion. A lateral dimension of the top portion may be less than a lateral dimension of the bottom portion. An end of the top portion that may be facing away from the memory stack laterally exceeds the bottom portion by a distance.Type: GrantFiled: December 26, 2019Date of Patent: January 10, 2023Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Xinxin Liu, Jingjing Geng, Zhu Yang, Chen Zuo, Xiangning Wang
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Publication number: 20230005959Abstract: A method for forming a three-dimensional (3D) memory device includes forming a dielectric stack including a plurality of first/second dielectric layer pairs over a substrate, forming a plurality of channel structures extending in a lateral direction in a core region of the dielectric stack, forming a staircase structure including a plurality of stairs extending along the lateral direction in a staircase region of the dielectric stack, forming a first drain-select-gate (DSG) cut opening extending in the lateral direction in the core region and a second DSG cut opening in the staircase region, and forming a first DSG cut structure in the first DSG cut opening and a second DSG cut structure in the second DSG cut opening.Type: ApplicationFiled: September 12, 2022Publication date: January 5, 2023Inventors: Jianzhong Wu, Zongke Xu, Jingjing Geng
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Patent number: 11502098Abstract: Embodiments of structures and methods for forming three-dimensional (3D) memory devices are provided. In an example, a 3D memory device includes a core region and a staircase region. The staircase region includes a plurality of stairs each has at least a conductor/dielectric pair extending in a lateral direction. The staircase region includes a drain-select-gate (DSG) cut structure extending along the lateral direction and a vertical direction, and a plurality of support structures extending in the DSG structure along the vertical direction. Of at least one of the support structures, a dimension along the lateral direction is greater than a dimension along a second lateral direction perpendicular to the lateral direction.Type: GrantFiled: May 22, 2020Date of Patent: November 15, 2022Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Jianzhong Wu, Zongke Xu, Jingjing Geng
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Publication number: 20220231043Abstract: Aspects of the disclosure provide semiconductor devices. For example, a semiconductor device includes a substrate having a first region and a second region along a first direction that is parallel to a main surface of the substrate. Then, the semiconductor device includes a memory stack that includes a first stack of alternating gate layers and insulating layers and a second stack of alternating gate layers and insulating layers along a second direction that is perpendicular to the main surface of the substrate. Further, the semiconductor device includes a joint insulating layer in the second region and a third stack of alternating gate layers and insulating layers in the first region between the first stack of alternating gate layers and insulating layers and the second stack of alternating gate layers and insulating layers.Type: ApplicationFiled: March 26, 2021Publication date: July 21, 2022Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Qiangwei ZHANG, Jingjing GENG, Bin YUAN, Xiangning WANG, Chen ZUO, Zhu YANG, Liming CHENG, Zhen GUO
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Publication number: 20220181349Abstract: Aspects of the disclosure provide methods for fabricating semiconductor devices. In some examples, a method for fabricating a semiconductor device includes forming a stack of layers having a first region and a second region. The stack of layers includes at least a first layer. The method then forms a hard mask layer on the stack of layers in the first region. Then, the method includes patterning the stack of layers in the second region of the semiconductor device. The patterning of the stack of layers in the second region removes a portion of the stack of layers in the second region, and exposes a side of the stack of layers. The method further includes covering at least the side of the stack of layers with a second layer that has a lower remove rate than the first layer, and then the method includes removing the hard mask layer.Type: ApplicationFiled: March 26, 2021Publication date: June 9, 2022Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Bin YUAN, Zhu YANG, Xiangning WANG, Chen ZUO, Jingjing GENG, Zhen GUO, Zongke XU, Qiangwei ZHANG
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Publication number: 20220149062Abstract: A semiconductor device is provided. The semiconductor device includes a stack of word line layers and insulating layers that are alternatingly arranged in a vertical direction perpendicular to a substrate of the semiconductor device. The stack includes a first array region and an adjacent first staircase region. The semiconductor device includes a dummy channel structure that extends in the vertical direction through the word line layers and the insulating layers in the first staircase region of the stack. At least one of the word line layers is located further away from a central axis of the dummy channel structure than the insulating layers adjacent to the at least one of the word line layers.Type: ApplicationFiled: January 27, 2021Publication date: May 12, 2022Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: QiangWei ZHANG, Jingjing GENG, Zongke XU
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Publication number: 20220085181Abstract: Aspects of the disclosure provide a method for fabricating a semiconductor device having an first stack of alternating insulating layers and sacrificial word line layers arranged over a substrate, the first stack including a core region and a staircase region. The method can include forming a first dielectric trench in the core region of the first stack, forming a second dielectric trench that is adjacent to and connected with the first dielectric trench in the staircase region of the first stack, and forming dummy channel structures extending through the first stack where the dummy channel structures are spaced apart from the second dielectric trench.Type: ApplicationFiled: December 23, 2020Publication date: March 17, 2022Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Hang YIN, Zhipeng WU, Kai HAN, Lu ZHANG, Pan WANG, Xiangning WANG, Hui ZHANG, Jingjing GENG, Meng XIAO
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Publication number: 20220077283Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack on the substrate, a plurality of channel structures each extending vertically through the memory stack, and one or more isolation structures. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. An outmost one of the conductive layers toward the substrate is a source select gate line (SSG). Each isolation structure surrounds at least one of the channel structures in a plan view to separate the SSG and the at least one channel structure.Type: ApplicationFiled: October 29, 2020Publication date: March 10, 2022Inventors: Jiajia Wu, Jingjing Geng, Yang Zhou, Zhen Guo, Meng Xiao, Hui Zhang
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Publication number: 20220077180Abstract: Three-dimensional (3D) memory devices and methods for forming the 3D memory devices are provided. In one example, a 3D memory device includes a substrate and a memory stack including interleaved conductive layers and dielectric layers on the substrate. The memory stack includes a core structure and a staircase structure. The staircase structure is on one side of the memory stack. The 3D memory device also includes a dummy channel structure extending vertically through the staircase structure. The dummy channel structure includes a plurality of sections along a vertical side of the dummy channel structure. The plurality of sections respectively interface with the interleaved conductive layers in the staircase structure. At least one of the plurality of sections includes a non-flat surface at an interface between the at least one of the plurality of sections and a corresponding conductive layer.Type: ApplicationFiled: October 29, 2020Publication date: March 10, 2022Inventors: Jianzhong Wu, Jingjing Geng
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Publication number: 20220077181Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack on the substrate, a plurality of channel structures each extending vertically through the memory stack, an isolation structure, and an alignment mark. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. An outmost one of the conductive layers toward the substrate is a source select gate line (SSG). The isolation structure extends vertically into the substrate and surrounds at least one of the channel structures in a plan view to separate the SSG and the at least one channel structure. The alignment mark extends vertically into the substrate and is coplanar with the isolation structure.Type: ApplicationFiled: October 29, 2020Publication date: March 10, 2022Inventors: Zhen Guo, Jingjing Geng, Bin Yuan, Jiajia Wu, Xiangning Wang, Zhu Yang, Chen Zuo
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Publication number: 20210335812Abstract: Embodiments of structures and methods for forming three-dimensional (3D) memory devices are provided. In an example, a 3D memory device includes a core region and a staircase region. The staircase region includes a plurality of stairs each has at least a conductor/dielectric pair extending in a lateral direction. The staircase region includes a drain-select-gate (DSG) cut structure extending along the lateral direction and a vertical direction, and a plurality of support structures extending in the DSG structure along the vertical direction. Of at least one of the support structures, a dimension along the lateral direction is greater than a dimension along a second lateral direction perpendicular to the lateral direction.Type: ApplicationFiled: June 11, 2021Publication date: October 28, 2021Inventors: Jianzhong Wu, Zongke Xu, Jingjing Geng
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Publication number: 20210335806Abstract: Embodiments of structures and methods for forming three-dimensional (3D) memory devices are provided. In an example, a 3D memory device includes a core region and a staircase region. The staircase region includes a plurality of stairs each has at least a conductor/dielectric pair extending in a lateral direction. The staircase region includes a drain-select-gate (DSG) cut structure extending along the lateral direction and a vertical direction, and a plurality of support structures extending in the DSG structure along the vertical direction. Of at least one of the support structures, a dimension along the lateral direction is greater than a dimension along a second lateral direction perpendicular to the lateral direction.Type: ApplicationFiled: May 22, 2020Publication date: October 28, 2021Inventors: Jianzhong Wu, Zongke Xu, Jingjing Geng