Patents by Inventor Jingjing Guo

Jingjing Guo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230381728
    Abstract: A catalytic reaction unit has a plurality of catalyst bed layers arranged vertically, each of the catalyst bed layers being filled with a solid catalyst, and an inclined surface on the upper part of the corresponding solid catalyst arranged between adjacent catalyst bed layers; a liquid phase feeding subunit arranged above the topmost catalyst bed layer, and the liquid phase feed is guided by the inclined surface to sequentially enter each catalyst bed layer from top to bottom; a gas phase feeding subunit arranged between the catalyst bed layer of an upper layer and the inclined surface of the next layer, and a gas phase channel relatively isolated from the gas phase feeding subunit. The gas phase product generated after the gas-phase feed and the liquid phase feed react in the catalyst bed layer directly enters the gas phase channel.
    Type: Application
    Filed: October 21, 2021
    Publication date: November 30, 2023
    Inventors: Yuzhuo ZHAO, Tao LIU, Bingbing GUO, Xiaobing HUANG, Genhai XUAN, Tong XU, Jingjing WANG
  • Publication number: 20230365558
    Abstract: A series of tetrahydroisoquinoline derivatives and the crystal forms thereof. Specifically disclosed are a compound as represented by formula (VII), a crystal form thereof, and a pharmaceutically acceptable salt thereof.
    Type: Application
    Filed: September 18, 2021
    Publication date: November 16, 2023
    Inventors: Kevin X CHEN, Zuhao GUO, Yanxin YU, Boyu HU, Jingjing WANG, Zhaoguo CHEN, Cheng XIE, Jian XIONG, Yongbo FANG, Yingtao LIU, Jian LI, Shuhui CHEN
  • Publication number: 20230363207
    Abstract: An array substrate, a preparing method thereof, a display panel and a display apparatus are disclosed. The array substrate includes: a base substrate (1); a driving circuit structure (2) on the base substrate (1); a planarization layer (3) and a plurality of electrode structures (4) successively located on a side, facing away from the base substrate (1), of the driving circuit structure (2); insulation structures (5) in gap areas between adjacent electrode structures (4); and pixel defining structures (6) on a side, facing away from the base substrate (1), of the insulation structures (5). The thickness of the insulation structures (5) is not smaller than the thickness of the electrode structures (4). An orthographic projection of the pixel defining structures (6) on the base substrate (1) at least completely covers the insulation structures (5).
    Type: Application
    Filed: December 29, 2020
    Publication date: November 9, 2023
    Inventors: Wei LI, Jingjing XIA, Bin ZHOU, Shengping DU, Yang ZHANG, Wei SONG, Qinghua GUO
  • Patent number: 11780097
    Abstract: There is provided an information processing apparatus including a reality determiner that determines whether an object detected on the basis of sensing data is a real object or an unreal object, and a controller that performs predetermined control on the basis of a result of the determination made by the reality determiner.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: October 10, 2023
    Inventors: Jingjing Guo, Sayaka Watanabe, Jun Yokono, Natsuko Ozaki, Jianing Wu
  • Patent number: 11774423
    Abstract: The invention discloses a parallel device and method for high-precision determination of sulfur solubility under multiple influencing factors, and the device comprises an elemental sulfur absorption system, an elemental sulfur saturation system and a sulfur content determination system. The elemental sulfur absorption system is used to remove the dissolved elemental sulfur in the sour gas. The elemental sulfur saturation system is arranged in parallel to saturate sour gases at different temperatures and pressures at the same time. The elemental sulfur absorption system and the elemental sulfur saturation system are arranged in parallel. The sulfur content determination system is used to determine the total sulfur content of the parallel elemental sulfur saturation system and the elemental sulfur content in the sour gas after absorbing the elemental sulfur under the same conditions.
    Type: Grant
    Filed: December 28, 2022
    Date of Patent: October 3, 2023
    Assignee: Southwest Petroleum University
    Inventors: Xiao Guo, Binliang Jiang, Jingjing Ma, Tao Li, Pengkun Wang, Changqing Jia, Ming Zhou, Yi He
  • Patent number: 11773155
    Abstract: The present application provides a bispecific antibody against rabies virus, and an application thereof. The bispecific antibody comprises two antigen-binding fragments binding to different epitopes of G protein of rabies virus, and has rabies virus neutralization activity.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: October 3, 2023
    Assignees: Beijing Wisdomab Biotechnology Co., ltd, GENRIX (Shanghai) Biopharmaceutical Co., Ltd., Chongqing GENRIX Biopharmaceutical Co., Ltd.
    Inventors: Zhigang Liu, Xiaobo Hao, Yulan Liu, Jingjing Guo
  • Publication number: 20230307557
    Abstract: An integrated circuit includes an SOI substrate having a semiconductor layer over a buried insulator layer; the semiconductor layer contains white space regions that include a PWELL region. An electronic device includes an NWELL region in the semiconductor layer, a dielectric over the NWELL region, and a polysilicon plate over the dielectric. A sacrificial NWELL ring is adjacent to and separated from the NWELL region by a first gap.
    Type: Application
    Filed: February 5, 2022
    Publication date: September 28, 2023
    Inventors: Honglin Guo, Zachary K Lee, Jingjing Chen
  • Publication number: 20230301106
    Abstract: Embodiments of three-dimensional (3D) memory devices are disclosed. In an example, a 3D memory device includes a semiconductor layer, a memory stack over the semiconductor layer, first channel structures each extending vertically through the memory stack in an edge region, and an isolation structure. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. At least one of conductive layers toward the semiconductor layer is a source select gate line (SSG). The isolation structure extends vertically through the SSG and into the semiconductor layer. The memory stack includes a core array region, a staircase region, and the edge region being laterally between the core array region and the staircase region. At least one of the first channel structures extends through the isolation structure and is separated from the SSG through the isolation structure.
    Type: Application
    Filed: May 25, 2023
    Publication date: September 21, 2023
    Inventors: Zhen Guo, Jingjing Geng, Bin Yuan, Jiajia Wu, Xiangning Wang, Zhu Yang, Chen Zuo
  • Patent number: 11735476
    Abstract: A semiconductor structure and its fabrication method are provided. The method includes: providing a substrate and a first metal layer in the substrate; forming a dielectric layer with a first opening exposing a portion of a top surface of the first metal layer on the substrate; bombarding the portion of the top surface of the first metal layer exposed by the first opening, by using a first sputtering treatment, to make metal materials on the top surface of the first metal layer be sputtered onto sidewalls of the first opening to form a first adhesion layer; and forming a second metal layer on a surface of the first adhesion layer and on the exposed portion of the top surface of the first metal layer using a first metal selective growth process.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: August 22, 2023
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Hailong Yu, Jingjing Tan, Xuezhen Jing, Wen Guo
  • Publication number: 20230257499
    Abstract: A preparation method for a copolymer includes the step(s) of contacting an olefin and an unsaturated carboxylic acid shown in Formula II or a derivative of the unsaturated carboxylic acid shown in Formula II with a catalyst and optionally a chain transfer agent for reaction in the presence of an alkane solvent to obtain the copolymer. The copolymer is a spherical and/or spherical-like copolymer.
    Type: Application
    Filed: April 21, 2023
    Publication date: August 17, 2023
    Inventors: Rong GAO, Zifang GUO, Junling ZHOU, Dongbing LIU, Jie FU, Jingjing LAI, Tingjie HUANG, Shiyuan XU, Xinyang LI
  • Publication number: 20230245402
    Abstract: There is provided an image processing device including: a data storage unit storing feature data indicating a feature of appearance of one or more physical objects; an environment map building unit for building an environment map based on an input image obtained by imaging a real space and the feature data, the environment map representing a position of a physical object present in the real space; a control unit for acquiring procedure data for a set of procedures of operation to be performed in the real space, the procedure data defining a correspondence between a direction for each procedure and position information designating a position at which the direction is to be displayed; and a superimposing unit for generating an output image by superimposing the direction for each procedure at a position in the input image determined based on the environment map and the position information, using the procedure data.
    Type: Application
    Filed: April 11, 2023
    Publication date: August 3, 2023
    Inventors: Yasuhiro SUTO, Masaki FUKUCHI, Kenichirou OOI, Jingjing GUO, Kouichi MATSUDA
  • Patent number: 11711921
    Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack on the substrate, a plurality of channel structures each extending vertically through the memory stack, an isolation structure, and an alignment mark. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. An outmost one of the conductive layers toward the substrate is a source select gate line (SSG). The isolation structure extends vertically into the substrate and surrounds at least one of the channel structures in a plan view to separate the SSG and the at least one channel structure. The alignment mark extends vertically into the substrate and is coplanar with the isolation structure.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: July 25, 2023
    Inventors: Zhen Guo, Jingjing Geng, Bin Yuan, Jiajia Wu, Xiangning Wang, Zhu Yang, Chen Zuo
  • Patent number: 11700837
    Abstract: The present application relates to a pet safety management method and system, computer equipment and a storage medium. The method includes: acquiring a first video comprising a target pet and a target object, the target object being an active object except the target pet; analyzing the first video to determine a first state of the target pet and a second state of the target object; acquiring a surrounding environment video of the target pet if the target pet is determined to be in an initial dangerous state according to the first state and the second state; and analyzing the surrounding environment, determining that the target pet is in a dangerous state if the surrounding environment is an interference-free environment, and controlling an warning device carried by the target pet to send a warning message to timely prevent a pet from being stolen.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: July 18, 2023
    Assignee: Xingchongwangguo (Beijing) Technology Co., Ltd
    Inventors: Cheng Song, Baoguo Liu, Jinyou Hu, Hao Wu, Kaiyan Liang, Weipeng Guo, Hai Li, Jingjing Gong
  • Patent number: 11696584
    Abstract: The present disclosure discloses a Streptomyces antioxidans strain Sa-21, namely, strain Sa-21 with an accession number of CCTCC NO: M 2020423. The present disclosure also discloses the use of the aforementioned Strepiomyces antioxidans strain Sa-21 in inhibition of Alternaria solani (A. solani). The Streptomyces antioxidans strain also has an inhibiting effect on both plant pathogenic fungi and plant pathogenic bacteria.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: July 11, 2023
    Assignee: Zhejiang Normal University
    Inventors: Donghua Jiang, Xin Guo, Jingjing Ma, Jingjing Zhang, Zhipeng He
  • Publication number: 20230212287
    Abstract: A bispecific antibody, which comprises an antigen-binding portion against human CD3E and/or an antigen-binding portion against human BCMA. Additionally, provided are medical and biological uses of the bispecific antibody.
    Type: Application
    Filed: August 27, 2019
    Publication date: July 6, 2023
    Inventors: Zhigang Liu, Shunar Wan, Yulan Liu, Xiaobe HAO, Junjie Hu, Jingjing Guo
  • Publication number: 20230194446
    Abstract: An X-ray-based test device for a plugging removal effect of a sulfur dissolvent on a sulfur deposition rock sample includes a constant speed and pressure pump, a first intermediate container, a second intermediate container, a first pressure transmitter, a core holder, a second pressure transmitter, a first electric pump, a third intermediate container, a back-pressure valve, a gas flow meter, an H2S neutralization tank, a second electric pump, a back-pressure transmitter, a confining pressure transmitter, an X-ray generator, an X-ray detector and a thermotank. A sour gas sample is placed in the first intermediate container, and nitrogen is filled in the second intermediate container. The sulfur dissolvent is placed into the third intermediate container. A confining pressure inlet is formed in the core holder. The test device may be used for evaluating the plugging removal effect of the sulfur dissolvent injected into the sulfur deposition rock sample.
    Type: Application
    Filed: December 16, 2022
    Publication date: June 22, 2023
    Applicant: Southwest Petroleum University
    Inventors: Xiao GUO, Pengkun WANG, Tao LI, Jingjing MA, Changqing JIA, Li ZHOU, Ming ZHOU, Yi HE, Bing KONG, Linkai LI, Lan WANG
  • Publication number: 20230194724
    Abstract: A high-dynamic-range hybrid solid-state lidar system, which is based on a transponder array module, includes a transmitting system, a transceiver integrated optical system, a one-dimensional scanning device, a detecting system, and an information processing system. An information processing control circuit and a gain control module increase a total amplification factor, in a single timing period, of a gain circuit over time, thereby alleviating an echo signal intensity distortion, and expanding a dynamic ranging range. The system uses the one-dimensional scanning device and the transceiver integrated optical system composed of a circulator, a lens set, and an optical fiber array, so that the optical system is separated from an avalanche photo diode (APD) detector, and focusing is not required. A temperature of a linear APD array is monitored in the detecting system to adjust a reverse bias voltage of an APD correspondingly and alleviate unstable gain caused by a temperature change.
    Type: Application
    Filed: May 9, 2022
    Publication date: June 22, 2023
    Applicant: Beijing Institute of Technology
    Inventors: Qun HAO, Jie CAO, Jingjing LI, Kun LI, Jiaqi GUO, Kaili ZHANG
  • Publication number: 20230174863
    Abstract: The present disclosure relates to the field of preparation of compound semiconductor nanomaterials, and in particular to a method for in-situ modification of mercury quantum dots in a traditional thermal injection process. It is characterized in that, in the traditional thermal injection process for synthesis of HgTe quantum dots, after a certain reaction time, a low boiling point polar solvent that is incompatible with a reaction solvent is rapidly injected, so that an interfacial separation of two liquid phases occurs in a mixed reaction, and then a selective crystal oriented surface modification is conducted on surfaces of mercury quantum dots.
    Type: Application
    Filed: November 9, 2022
    Publication date: June 8, 2023
    Inventors: Jingjing Liu, Jianlu Wang, Tianle Guo, Xinning Huang, Xiangjian Meng, Hong Shen, Tie Lin, Junhao Chu
  • Publication number: 20230167196
    Abstract: The invention discloses an anti-phenacetin monoclonal antibody hybridoma cell strain AD, a preparation method and application thereof, and relates to the technical field of food safety immunodetection. The monoclonal antibody hybridoma cell strain is named monoclonal cell strain AD and the number CGMCC19681. The Phe-BA obtained by the hydrolysis of the reaction product of the phenacetin metabolite acetaminophen and ethyl 4-bromobutyrate is used as the hapten, and the hapten is coupled with the carrier protein to prepare the immunogen Phe-BA-BSA. After the mice were immunized with the immunogen Phe-BA-BSA, they were fused with myeloma cells by PEG method, screened by indirect competitive enzyme-linked immunosorbent assay and subcloned five times to obtain hybridoma cell lines. The monoclonal antibody secreted by the cell line can be made into a phenacetin detection kit, which has good affinity and detection sensitivity for phenacetin, and can be used for immunodetection of phenacetin residues in food.
    Type: Application
    Filed: November 9, 2021
    Publication date: June 1, 2023
    Inventors: Chuanlai XU, Jingjing YAO, Hua KUANG, Liguang XU, Maozhong SUN, Xiaoling WU, Liqiang LIU, Wei MA, Jianping ZHU, Changlong HAO, Shanshan SONG, Yongming HU, Aihong WU, Lingling GUO, Xinxin XU
  • Publication number: 20230153502
    Abstract: It discloses a statistical timing analysis method of an integrated circuit under an advanced process and a low voltage. By simulating the fluctuation of process parameters of the integrated circuit under the advanced process, a statistical circuit timing model is built based on the relationship between the delay of the integrated circuit under the low voltage and the process parameters, and the maximum delay and the minimum delay under timing fluctuation of the integrated circuit are analyzed.
    Type: Application
    Filed: February 24, 2020
    Publication date: May 18, 2023
    Inventors: Peng CAO, Tai YANG, Jingjing GUO