Abstract: A system for a sandy soil landfill solid waste polluted river channel, includes a ground water interception and diversion system and a river channel ecological remediation system. The ground water interception and diversion system includes a water intake well arranged upstream of ground water in a landfill area, a buffer pool communicated with the water intake well, and a wastewater treatment system communicated with the buffer pool. The water intake well, the buffer pool, and the wastewater treatment system are communicated through a wastewater pipe. An electric wastewater valve and a variable frequency water pump are arranged on the wastewater pipe in sequence. The river channel ecological remediation system includes an impermeable layer arranged at a bottom of a river channel and ecological bank protections arranged on both sides of a river channel slope.

Abstract: The present application discloses a display substrate and a display apparatus. The display substrate includes: a base substrate, a first conductive layer, first insulating layer, second conductive layer, second insulating layer, and third conductive layer; the first conductive layer includes gate lines; the second conductive layer includes touch electrode wires; the orthographic projection of the touch electrode wires intersects with the orthographic projection of the gate lines; the second insulating layer has a first via hole, the third conductive layer is electrically connected to the touch electrode wires by the first via hole; the first via hole includes an upper opening and a lower opening communicating with each other, the lower opening is close to the base substrate, the upper opening is close to the third conductive layer; the orthographic projection of the lower opening does not overlap with the orthographic projection of the edge of the gate lines.

Abstract: An array substrate, a display panel, a display device, and a manufacturing method for an array substrate are provided. The array substrate includes a pixel unit group which includes a first pixel and a second pixel; the first pixel includes a first pixel electrode, a first switching element, and a first connection portion extending and protruding from the first pixel electrode; the second pixel includes a second pixel electrode, a second switching element, and a second connection portion extending and protruding from the second pixel electrode; the first pixel electrode and the first switching element are electrically connected to each other via the first connection portion; the second pixel electrode and the second switching element are electrically connected to each other via the second connection portion; and an extension length of the first connection portion is not equal to an extension length of the second connection portion.

Abstract: An array substrate, a display panel, a display device, and a manufacturing method for an array substrate are provided. The array substrate includes a pixel unit group which includes a first pixel and a second pixel; the first pixel includes a first pixel electrode, a first switching element, and a first connection portion extending and protruding from the first pixel electrode; the second pixel includes a second pixel electrode, a second switching element, and a second connection portion extending and protruding from the second pixel electrode; the first pixel electrode and the first switching element are electrically connected to each other via the first connection portion; the second pixel electrode and the second switching element are electrically connected to each other via the second connection portion; and an extension length of the first connection portion is not equal to an extension length of the second connection portion.

Abstract: This disclosure relates to the field of display technologies, and specifically to a display panel, a method for forming the same and a display device. The display panel includes an array substrate; a counter substrate aligned with the array substrate; and a parallel plate capacitor for realizing signal transmission between the array substrate and the counter substrate. Two capacitive plates of the parallel plate capacitor are located on opposite surfaces of the array substrate and the counter substrate respectively. Thus, conduction between the array substrate and the counter substrate is realized, and existing problems such as non-uniform cell thickness and light leakage caused by such conduction realized through conductive gold balls and so on are eliminated.

Abstract: A touch screen, a display device and a fabrication method of a touch screen are provided. The touch screen includes a gate layer, an insulating layer, a source-drain electrode layer, a first Indium Tin Oxide (ITO) layer, a protective layer and a second ITO layer. The insulating layer is overlaid on the gate layer, the source-drain electrode layer is overlaid on the insulating layer, the first ITO layer is overlaid on the source-drain electrode layer, the protective layer is overlaid on the first ITO layer, and the second ITO layer is overlaid on the protective layer; the gate layer includes a touch driving electrode, the source-drain electrode layer includes a touch sensing electrode line, and the second ITO layer includes a touch sensing electrode pattern.

Abstract: This disclosure relates to the field of display technologies, and specifically to a display panel, a method for forming the same and a display device. The display panel includes an array substrate; a counter substrate aligned with the array substrate; and a parallel plate capacitor for realizing signal transmission between the array substrate and the counter substrate. Two capacitive plates of the parallel plate capacitor are located on opposite surfaces of the array substrate and the counter substrate respectively. Thus, conduction between the array substrate and the counter substrate is realized, and existing problems such as non-uniform cell thickness and light leakage caused by such conduction realized through conductive gold balls and so on are eliminated.

Abstract: A touch screen, a display device and a fabrication method of a touch screen are provided. The touch screen includes a gate layer, an insulating layer, a source-drain electrode layer, a first Indium Tin Oxide (ITO) layer, a protective layer and a second ITO layer. The insulating layer is overlaid on the gate layer, the source-drain electrode layer is overlaid on the insulating layer, the first ITO layer is overlaid on the source-drain electrode layer, the protective layer is overlaid on the first ITO layer, and the second ITO layer is overlaid on the protective layer; the gate layer includes a touch driving electrode, the source-drain electrode layer includes a touch sensing electrode line, and the second ITO layer includes a touch sensing electrode pattern.

Abstract: An electronic detonator control chip (100) includes a communication interface circuit (101), a rectification bridge circuit (102), a charging circuit (103), a charging control circuit (110), a power management circuit (104), a firing control circuit (105), a logic control circuit (106), a non-volatile memory (107), a reset circuit (111), a safe discharging circuit (108), and a clock circuit (202). Wherein, the communication interface circuit (101) includes a data modulation module (210) and a data demodulation module (211) including two data demodulation circuits (212). The logic control circuit (106) further includes a programmable delay module (281), an input/out interface (282), a serial communication interface (283), a prescaler (284), a CPU (285), and so on.

Abstract: An electronic detonator control chip (100) includes a communication interface circuit (101), a rectification bridge circuit (102), a charging circuit (103), a charging control circuit (110), a power management circuit (104), a firing control circuit (105), a logic control circuit (106), a non-volatile memory (107), a reset circuit (111), a safe discharging circuit (108), and a clock circuit (202). Wherein, the communication interface circuit (101) includes a data modulation module (210) and a data demodulation module (211) including two data demodulation circuits (212). The logic control circuit (106) further includes a programmable delay module (281), an input/out interface (282), a serial communication interface (283), a prescaler (284), a CPU (285), and so on.