Abstract: An optical receiver includes: an active transimpedance amplifier (TIA) that converts a photocurrent from a photosensor into an active voltage signal; a high-speed amplifier that amplifies the active voltage signal to produce an amplified voltage signal that comprises an output for the optical receiver; and a reference-voltage-generation circuit that generates a reference voltage for the high-speed amplifier. This reference-voltage-generation circuit includes a dummy TIA that is identical to the active TIA, but does not receive a live input signal, and produces a dummy voltage signal. It also includes a low-speed amplifier which includes: an active input that receives the active voltage signal from the active TIA output; a dummy input that receives the dummy voltage signal from the dummy TIA output; and an output that controls directly or indirectly the reference voltage for the high-speed amplifier.

Abstract: The disclosed embodiments relate to the design of an equalizer that uses both cross-coupled cascodes and inductive peaking to reduce distortion in a signal received from a communication channel by attenuating lower frequencies and amplifying higher frequencies. At lower frequencies, when the effects of inductive impedance within the equalizer are negligible, the equalizer essentially functions as a traditional cascode amplifier that presents high gain. At higher frequencies, the increases in inductive impedances within the equalizer act to boost a gain of the equalizer.

Abstract: A static frequency divider circuit includes a first and second latch that are interconnected by a series path circuit and by a feedback path circuit. Each of the latches includes a reading BALLSACKbranch and a latching branch. The series path circuit includes a push-pull current driver to speed state transitions between the latching branch of the first latch and the reading branch of the second latch. Similarly, feedback path circuit includes a push-pull current driver to speed state transitions between the latching branch of the second latch and the reading branch of the first latch.

Abstract: A static frequency divider circuit includes a first and second latch connected in series and a feedback path. Each of the latches includes a reading branch and a latching branch. The divider circuit further includes an inter-latch circuit that is connected between the latching branch of the first latch and the reading branch of the second latch. The inter-latch circuit is connected so as to reduce the current needs of the latching branches in both the first and second latches.

Abstract: A static frequency divider circuit includes a first and second latch that are interconnected by a series path circuit and by a feedback path circuit. Each of the latches includes a reading branch and a latching branch. The series path circuit includes a push-pull current driver to speed state transitions between the latching branch of the first latch and the reading branch of the second latch. Similarly, feedback path circuit includes a push-pull current driver to speed state transitions between the latching branch of the second latch and the reading branch of the first latch.

Abstract: A static frequency divider circuit includes a first and second latch connected in series and a feedback path. Each of the latches includes a reading branch and a latching branch. The divider circuit further includes an inter-latch circuit that is connected between the latching branch of the first latch and the reading branch of the second latch. The inter-latch circuit is connected so as to reduce the current needs of the latching branches in both the first and second latches.