Patents by Inventor Jingtao XIE

Jingtao XIE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240389324
    Abstract: A semiconductor structure, a fabrication method thereof and a memory system are provided. The method includes: forming a stack of layers having a first surface; forming a channel structure extending through the stack of layers in a stacking direction, and comprising a channel layer and a plug structure electrically connected with the channel layer, wherein the plug structure is located close to the first surface and comprising an exposed surface; oxidizing the exposed surface of the plug to form a protruding structure, a surface of the protruding structure protruding above the first surface; forming an upper select gate layer on the first surface, the upper select gate layer covering the protruding structure; and forming an upper select channel structure extending through the upper select gate layer and the protruding structure in the stacking direction, and being in contact with the plug structure.
    Type: Application
    Filed: December 13, 2023
    Publication date: November 21, 2024
    Inventors: Zhibin Liu, Jingtao Xie, Wenxi Zhou
  • Publication number: 20240224517
    Abstract: A method for forming a three-dimensional (3D) memory device is disclosed. A stack structure including interleaved first dielectric layers and second dielectric layers is formed. Channel structures extending through the first dielectric layers and the second dielectric layers in a first region of the stack structure are formed. All the second dielectric layers in the first region and parts of the second dielectric layers in a second region of the stack structure are replaced with conductive layers. Word line pick-up structures extending through the first dielectric layers and remainders of the second dielectric layers in the second region of the stack structure are formed at different depths. A portion of the second dielectric layers in the second region that is closest to the opening is converted into a dielectric material different from the material of the second dielectric layers.
    Type: Application
    Filed: January 4, 2023
    Publication date: July 4, 2024
    Inventors: Yang Chen, Di Wang, Jingtao Xie, Qingfu Zhang, Zhiliang Xia, Zongliang Huo
  • Publication number: 20240188292
    Abstract: In certain aspects, a three-dimensional (3D) memory device includes channel structures in a first region, word line pick-up structures in a second region, and word lines each extending from the first region into at least a portion of the second region. At least one word line pick-up structure includes multiple sections each electrically connected to a different word line.
    Type: Application
    Filed: December 29, 2022
    Publication date: June 6, 2024
    Inventors: Cuicui Kong, Kun Zhang, Yuhui Han, Linchun Wu, Shuangshuang Wu, Zhiliang Xia, Zongliang Huo, Jingtao Xie, Bingjie Yan, Di Wang, Wenxi Zhou
  • Publication number: 20240064978
    Abstract: A three-dimensional (3D) memory device includes a stack, a plurality of contact structures, and a plurality of support structures. The stack in an insulating structure includes a plurality of conductive layers and a plurality of dielectric layers stacked alternatingly, and the stack includes a staircase structure. The plurality of contact structures each extends through the insulating structure and in contact with a respective conductive layer of the plurality of conductive layers in the staircase structure. The plurality of support structures extends through the stack in the staircase structure. Each support structure is in contact with one of the plurality of contact structures.
    Type: Application
    Filed: August 18, 2022
    Publication date: February 22, 2024
    Inventors: Jingtao Xie, Bingjie Yan, Kun Zhang, Wenxi Zhou, Zhiliang Xia, Zongliang Huo
  • Publication number: 20240063140
    Abstract: A three-dimensional (3D) memory device includes a stack, a plurality of contact structures, and a plurality of support structures. The stack in an insulating structure includes conductive layers and dielectric layers stacked alternatingly, and the stack includes a staircase structure. Each contact structure extends through the insulating structure and is in contact with a respective conductive layer in the staircase structure. The support structures extend through the stack in the staircase structure. The contact structures are arranged in a first row and a second row, the first row of contact structures is in electrical contact with the peripheral device, and the second row of contact structures is in electrical insulation with the peripheral device.
    Type: Application
    Filed: August 18, 2022
    Publication date: February 22, 2024
    Inventors: Jingtao Xie, Bingjie Yan, Kun Zhang, Wenxi Zhou, Zhiliang Xia, Zongliang Huo
  • Publication number: 20240032288
    Abstract: A 3D includes a memory array structure. The memory array structure includes a first memory array structure and a second memory array structure each having a plurality of conductive/dielectric layer pairs. The memory array structure also includes a staircase structure between the first memory array structure and the second memory array structure. The staircase structure includes a first staircase zone and a second staircase zone. The first staircase zone includes at least one staircase, each including a plurality of stairs. The second staircase zone includes a bridge structure, and at least one other staircase over the bridge structure. The bridge structure connects the first memory array structure and the second memory array structure, the at least one other staircase each including a plurality of stairs. At least one stair in one or more of the at least one staircase is electrically connected to the bridge structure.
    Type: Application
    Filed: July 19, 2022
    Publication date: January 25, 2024
    Inventors: Jingtao Xie, Bingjie Yan, Wenxi Zhou, Zhiliang Xia, Zongliang Huo
  • Publication number: 20230420372
    Abstract: Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a stack structure and a contact structure. The stack structure comprises interleaved gate layers and insulating layers. The contact structure comprises a conductive structure and one or more insulating structures. The conductive structure can extend through the stack structure and form a conductive connection with one of the gate layers. The one or more insulating structures surround the conductive structure and electrically isolate the conductive structure from remaining ones of the gate layers. The one or more insulating structures further include one or more first insulating structures. Each of the one or more first insulating structures is disposed between an adjacent pair of the insulating layers, and the one or more first insulating structures are disposed on a first side of the one of the gate layers.
    Type: Application
    Filed: June 23, 2022
    Publication date: December 28, 2023
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Jingtao XIE, Bingjie YAN, Wenxi ZHOU, Di WANG, Zhiliang XIA, Zongliang HUO