Abstract: Coated and expanded, nanofiber structures are provided and methods of use thereof.

Abstract: A high-definition map building method includes determining a key node describing information about a key position of a lane attribute change, determining a key node layer based on a position of the key node and an attribute of the key node, and determining a high-definition map based on a navigation map and the key node layer. The navigation map provides road-level navigation information, and the high-definition map provides lane-level navigation information.

Abstract: Disclosed is a food processing apparatus having a food processing chamber, comprising a blade arrangement and a motor arranged to drive the blade arrangement. The blade arrangement comprises a body having a surface arrangement delimiting a cavity and a plurality of cutting blades extending from the surface arrangement into the cavity.

Abstract: A method for programming a memory. The method includes providing a memory structure with a floating gate, and grounding a source of the memory structure; applying voltages to a drain and a bulk, forming an electric field, generating electron-hole pairs, and generating primary electrons, wherein the voltage applied to the bulk is lower than the voltage applied to the drain; making holes accelerate downward under the action of the electric field and collide with the bulk in the memory structure within a predetermined time to generate secondary electrons; applying voltages to a gate and the bulk respectively, where the voltage applied to the bulk is lower than the voltage applied to the gate, to enable the secondary electrons to generate tertiary electrons under the action of an electric field in a vertical direction, and the tertiary electrons are injected into the floating gate to complete a programming operation.

Abstract: Embodiments of this application provide an image transmission method and apparatus.

Abstract: The present disclosure relates to a method for programming flash memory, which includes: providing a flash memory structure having a floating gate, and floating a source of the flash memory structure; separately applying voltages to a drain and a substrate, to form an electric field, and generating electron-hole pairs, to generate primary electrons, where the voltage applied to the substrate is less than the voltage applied to the drain; accelerating holes downward under the action of the electric field to collide with the substrate in the flash memory structure within a preset time, to generate secondary electrons; and separately applying voltages to a gate and the substrate, where the voltage applied to the substrate is less than the voltage applied to the gate, and enabling the secondary electrons to generate tertiary electrons to inject the tertiary electrons into the floating gate, to complete a programming operation.

Abstract: The present disclosure provides a method for programming charge trap flash memory, including: enabling a channel of a charge trap storage component, to form a transverse electric field between a source and a drain, to generate primary electrons flowing from the source to the drain; colliding, by the primary electrons after a preset time, with the drain to generate electron holes; applying voltages to the drain and a substrate, where the electron holes are accelerated downward by the action of the electric field to collide with the substrate, to generate secondary electrons; and applying voltages to a gate and the substrate, to form a vertical electric field, wherein the secondary electrons generate tertiary electrons under the action of the vertical electric field and the tertiary electrons are injected into an insulating storage medium layer of the charge trap storage component, to complete a programming operation.

Abstract: The present disclosure relates to a method for programming a 3D NAND flash memory, which includes: S1) providing a 3D flash memory array, and eliminating residual charges; S2) strobing a bit line where an upper sub-storage module is located; S3) applying a drain voltage to the drain of a to-be-programmed memory cell, and floating a source thereof; S4) applying a programming voltage to the gate of the to-be-programmed memory cell, to complete programming; and S5) after completing the programming of the upper sub-storage module, and when the upper sub-storage module keeps a programmed state, strobing a bit line where a lower sub-storage module is located, and repeating operation S3) and operation S4) to achieve programming of the lower sub-storage module. In the method for programming a 3D NAND flash memory according to the present disclosure, programming is completed based on tertiary electron collision.

Abstract: The present disclosure relates to a method for programming a NAND flash memory, which includes: providing a NAND flash memory array, and initializing a to-be-programmed memory cell; applying a drain voltage to the drain of the to-be-programmed memory cell, and floating the source of the to-be-programmed memory cell; and applying a programming voltage to the gate of the to-be-programmed memory cell, and discharging the voltage at each end of the to-be-programmed memory cell after maintaining the voltage for a first time period, to complete programming; a difference between the voltage applied to the drain and the voltage applied to the substrate of the to-be-programmed memory cell being not less than 4 V, the first time period being not longer than 100 ?s, and the programming voltage being not higher than 10 V.

Abstract: A method for programming a B4 flash memory includes: floating a source of a P-channel flash memory device; separately applying voltages to a gate, a drain, and a bulk of the P-channel flash memory device, and injecting holes into the bulk, so that electrons are gathered in the drain to form primary electrons; separately applying voltages to the drain and the bulk, so that an electric field is formed between the drain and the bulk, where the holes accelerate downward under the action of the electric field and impact the bulk in the P-channel flash memory device to generate secondary electrons; and separately applying voltages to the gate and the bulk of the P-channel flash memory device, so that the secondary electrons form tertiary electrons under the action of the electric field in a vertical direction, where the tertiary electrons are superposed with the primary electrons to be injected into a floating gate.

Abstract: A method for programming a B4 flash memory includes: floating a source of a P-channel flash memory device; separately applying voltages to a gate, a drain, and a bulk of the P-channel flash memory device, and injecting holes into the bulk, so that electrons are gathered in the drain to form primary electrons; separately applying voltages to the drain and the bulk, so that an electric field is formed between the drain and the bulk, where the holes accelerate downward under the action of the electric field and impact the bulk in the P-channel flash memory device to generate secondary electrons; and separately applying voltages to the gate and the bulk of the P-channel flash memory device, so that the secondary electrons form tertiary electrons under the action of the electric field in a vertical direction, where the tertiary electrons are superposed with the primary electrons to be injected into a floating gate.

Abstract: A method for programming a memory. The method includes providing a memory structure with a floating gate, and grounding a source of the memory structure; applying voltages to a drain and a bulk, forming an electric field, generating electron-hole pairs, and generating primary electrons, wherein the voltage applied to the bulk is lower than the voltage applied to the drain; making holes accelerate downward under the action of the electric field and collide with the bulk in the memory structure within a predetermined time to generate secondary electrons; applying voltages to a gate and the bulk respectively, where the voltage applied to the bulk is lower than the voltage applied to the gate, to enable the secondary electrons to generate tertiary electrons under the action of an electric field in a vertical direction, and the tertiary electrons are injected into the floating gate to complete a programming operation.

Abstract: The present disclosure provides a method for programming charge trap flash memory, including: enabling a channel of a charge trap storage component, to form a transverse electric field between a source and a drain, to generate primary electrons flowing from the source to the drain; colliding, by the primary electrons after a preset time, with the drain to generate electron holes; applying voltages to the drain and a substrate, where the electron holes are accelerated downward by the action of the electric field to collide with the substrate, to generate secondary electrons; and applying voltages to a gate and the substrate, to form a vertical electric field, wherein the secondary electrons generate tertiary electrons under the action of the vertical electric field and the tertiary electrons are injected into an insulating storage medium layer of the charge trap storage component, to complete a programming operation.

Abstract: The present disclosure relates to a method for programming a 3D NAND flash memory, which includes: S1) providing a 3D flash memory array, and eliminating residual charges; S2) strobing a bit line where an upper sub-storage module is located; S3) applying a drain voltage to the drain of a to-be-programmed memory cell, and floating a source thereof; S4) applying a programming voltage to the gate of the to-be-programmed memory cell, to complete programming; and S5) after completing the programming of the upper sub-storage module, and when the upper sub-storage module keeps a programmed state, strobing a bit line where a lower sub-storage module is located, and repeating operation S3) and operation S4) to achieve programming of the lower sub-storage module. In the method for programming a 3D NAND flash memory according to the present disclosure, programming is completed based on tertiary electron collision.

Abstract: The present disclosure relates to a method for programming flash memory, which includes: providing a flash memory structure having a floating gate, and floating a source of the flash memory structure; separately applying voltages to a drain and a substrate, to form an electric field, and generating electron-hole pairs, to generate primary electrons, where the voltage applied to the substrate is less than the voltage applied to the drain; accelerating holes downward under the action of the electric field to collide with the substrate in the flash memory structure within a preset time, to generate secondary electrons; and separately applying voltages to a gate and the substrate, where the voltage applied to the substrate is less than the voltage applied to the gate, and enabling the secondary electrons to generate tertiary electrons to inject the tertiary electrons into the floating gate, to complete a programming operation.

Abstract: The present disclosure relates to a method for programming a NAND flash memory, which includes: providing a NAND flash memory array, and initializing a to-be-programmed memory cell; applying a drain voltage to the drain of the to-be-programmed memory cell, and floating the source of the to-be-programmed memory cell; and applying a programming voltage to the gate of the to-be-programmed memory cell, and discharging the voltage at each end of the to-be-programmed memory cell after maintaining the voltage for a first time period, to complete programming; a difference between the voltage applied to the drain and the voltage applied to the substrate of the to-be-programmed memory cell being not less than 4 V, the first time period being not longer than 100 ?s, and the programming voltage being not higher than 10 V.

Abstract: A hemostatic material or a tissue sealant, wherein a main component of the hemostatic material or the tissue sealant or part of the hemostatic material or the tissue sealant is a sponge grown in sea water or fresh water.

Abstract: Disclosed is a frame for a bogie, comprising two side beams parallel to each other and a transverse beam connected to the middles of the side beams, wherein the middle of the transverse beam is provided with a traction pin hole, and an upper surface of the transverse beam is provided with a plurality of mounting seats for mounting a secondary suspension. The frame of the present invention is provided with a traction pin hole at the center of the transverse beam so that the transverse beam is connected to the bolster so as to bear a traction force, and a plurality of mounting seats for mounting the secondary suspension are arranged on an upper surface of the transverse beam, so that the secondary suspension can bear a rotation movement between the bogie and the vehicle body to improve curve passing capability of the vehicle.

Abstract: The present disclosure belongs to the field of network technologies, and discloses a resource deduction method and apparatus, an intelligent terminal, and a deduction server. The method includes: sending a rule obtaining request for a deduction rule of a user-specified deduction item to the deduction server; receiving the deduction rule returned by the deduction server; calculating a second resource value that is obtained after applying the deduction rule to a first resource value associated with the user-specified deduction item; and sending a resource transfer request carrying the second resource value to the deduction server. The present disclosure resolves a problem that a merchant needs to manually calculate expense that is obtained after applying the deduction rule to the first resource, and payment efficiency is relatively low.

Abstract: Example methods and apparatus for quantizing a neural network model in a device are described. In one example method, user calibration data is obtained and input into the neural network model to calculate a quantization parameter of each of a plurality of layers of the neural network model. To-be-quantized data is input into the neural network model to quantize input data of each of the plurality of layers by using the quantization parameter of each of the plurality of layers. Because the user calibration data is generated based on data generated by the device used by a user, the quantization parameter can be obtained online, and the quantization parameter matches user data in the device.