Abstract: A control apparatus includes: a receiving circuit, configured to receive a read clock signal from the memory, and output the read clock signal; a clock circuit, configured to generate a first internal clock signal; a selection circuit, configured to receive the read clock signal and the first internal clock signal, and output one of the read clock signal and the first internal clock signal as a target read clock signal; and a latch circuit, configured to receive the target read clock signal and a read data signal sent by the memory, and perform latch processing on the read data signal by using the target read clock signal.

Abstract: A compress attached memory module includes: a compress attached memory circuit board; a plurality of memory chips, arranged on the compress attached memory circuit board; and a power management apparatus, arranged on the compress attached memory circuit board and electrically connected to the plurality of memory chips, wherein the power management apparatus includes a preset quantity of power management integrated circuits and is configured to provide electric energy generated by the preset quantity of power management integrated circuits to the plurality of memory chips as electric energy for power supply, wherein the preset quantity of the power management integrated circuits in the power management apparatus is preset according to power demand of the plurality of memory chips.

Abstract: Embodiments of the present disclosure provide a method for calibrating a sound velocity applied to a multi-layer variable thickness structure, comprising: constructing a planar multi-layer medium stacked structure and determining a sound velocity of each layer of medium material in the planar multi-layer medium stacked structure; establishing a curved multi-layer medium stacked structure, the curved multi-layer medium stacked structure being arranged with a plurality of discrete elements; at the same time, establishing a fluctuation equation for determining a sound pressure value of each of the plurality of discrete elements; establishing a loss function between the sound pressure value of each discrete element calculated by the fluctuation equation and a measured sound pressure value of each discrete element; performing a gradient descent calculation on the sound pressure value of each discrete element based on the loss function, iteratively updating to obtain a sound velocity value being used as a weighting

Abstract: Methods, systems, and devices for testing circuit for a memory device are described. An apparatus may include a memory system including contacts that route signals to different regions of the memory system. The apparatus may include a first substrate including a memory system interface coupled with the memory system and a probe interface. The apparatus may also include a second substrate coupled with a host system interface of the first substrate and receive the signal of the memory system from the memory system interface. The first interface may route a signal of the memory system to the probe interface and a tester to determine the signal's integrity and any errors associated with the memory system. The first substrate may include a resistor coupled with the contacts of the memory system, the resistor on a surface of the interface may be configured to improve the signal at the tester.

Abstract: The present disclosure provides an information transmission method, a memory, a control apparatus. The method includes: receiving a first target command sent from the outside; and outputting first duty cycle data of an internal data clock signal through a first group of data ports based on the first target command, where the first duty cycle data persists at the first group of data ports at least until a first stop command sent from the outside is received.

Abstract: Provided are an MBIST control circuit and method, a memory. The circuit includes: a memory control circuit, configured to receive an external precharge command of a target word line, generate a counter update command in response to the external precharge command, and output the counter update command; and a per row hammer tracking (PRHT) control circuit, configured to receive the counter update command, receive a PRHT control command, and stop providing the counter update command to a second output terminal of the PRHT control circuit when the PRHT control command is in a first level state, so that a row counter unit of the target word line connected to the second output terminal stops updating when no counter update command is received. The first level state of the PRHT control command is used to indicate a state of being in the MBIST test mode.

Abstract: A package structure and a semiconductor structure are provided. A ball grid array is disposed on a surface of a package substrate in the package structure, and the ball grid array includes multiple data ball grids. In a second direction, a maximum of two data ball grids are allowed to be consecutively arranged. The second direction is a row extension direction of the ball grid array.

Abstract: Methods, systems, and devices for testing circuit for a memory device are described. An apparatus may include a memory system including contacts that route signals to different regions of the memory system. The apparatus may include a first substrate including a memory system interface coupled with the memory system and a probe interface. The apparatus may also include a second substrate coupled with a host system interface of the first substrate and receive the signal of the memory system from the memory system interface. The first interface may route a signal of the memory system to the probe interface and a tester to determine the signal's integrity and any errors associated with the memory system. The first substrate may include a resistor coupled with the contacts of the memory system, the resistor on a surface of the interface may be configured to improve the signal at the tester.

Abstract: The present invention relates to methods of treating p53 wild type (WT) tumors. In particular, the invention provides novel therapies for p53 WT tumors based on the combination of Mouse Double Minute 2 (MDM2) inhibitors, e.g. HDM201, together with Casein Kinase 1 alpha (CK1?) degrading agents and/or an MDM4 inhibitors, e.g. lenalidomide. The combination may be used in the treatment of solid as well as hematologic p53 WT tumors, e.g. Merkel cell carcinoma (MCC) or myelodysplastic syndrome (MDS).

Abstract: Methods, systems, and devices for configurable memory die capacitance are described. A memory device may include a capacitive component, which may include one or more capacitors and associated switching components. The capacitive component may be coupled with an input/output (I/O) pad and an associated input buffer, and the one or more capacitors of the capacitive component may be selectively couplable with the I/O pad via the switching components. Switching components may be activated individually, in coordination, or not at all, such that one, multiple, or none of the capacitors may be coupled with the I/O pad. The capacitive component, I/O pad, and input buffer may be included in a same die of the memory device. In some cases, a configuration of the capacitive component may be based on signaling received from a host device.

Abstract: A clock system and a memory are disclosed. The clock system includes a system on chip (SoC) configured to generate a first oscillation signal, a second oscillation signal, a third oscillation signal and a fourth oscillation signal of a same frequency and amplitude. Further, the clock system includes a memory chip configured to output a data signal based on signal edges of the first oscillation signal, the second oscillation signal, the third oscillation signal and the fourth oscillation signal, and output a command/address signal based on the signal edges of the first oscillation signal and the third oscillation signal. The signal edges are rising edges or falling edges.

Abstract: Methods, systems, and devices for configurable memory die capacitance are described. A memory device may include a capacitive component, which may include one or more capacitors and associated switching components. The capacitive component may be coupled with an input/output (I/O) pad and an associated input buffer, and the one or more capacitors of the capacitive component may be selectively couplable with the I/O pad via the switching components. Switching components may be activated individually, in coordination, or not at all, such that one, multiple, or none of the capacitors may be coupled with the I/O pad. The capacitive component, I/O pad, and input buffer may be included in a same die of the memory device. In some cases, a configuration of the capacitive component may be based on signaling received from a host device.

Abstract: A clock system and a memory are disclosed. The clock system includes a system on chip (SoC) configured to generate a first oscillation signal, a second oscillation signal, a third oscillation signal and a fourth oscillation signal of a same frequency and amplitude. Further, the clock system includes a memory chip configured to output a data signal based on signal edges of the first oscillation signal, the second oscillation signal, the third oscillation signal and the fourth oscillation signal, and output a command/address signal based on the signal edges of the first oscillation signal and the third oscillation signal. The signal edges are rising edges or falling edges.

Abstract: Methods, systems, and devices for debug capabilities of a memory system with a pin are described. An apparatus may include a memory system that includes a plurality of pins of a first type that are configured to communicate information as part of operating the memory system and a pin of a second type. The apparatus may also include a circuit coupled with the memory system, the circuit including a resistor that is coupled with the pin of the second type. The memory system may include a controller that selects a value for the resistor and generates a code as part of a memory management operation to determine one or more operating conditions of the memory system based on selecting the value. The memory system controller may also determine an error associated with the code based on generating the code and the selected value of the resistor.

Abstract: A control apparatus includes: a receiving circuit, configured to receive a read clock signal from the memory, and output the read clock signal; a clock circuit, configured to generate a first internal clock signal; a selection circuit, configured to receive the read clock signal and the first internal clock signal, and output one of the read clock signal and the first internal clock signal as a target read clock signal; and a latch circuit, configured to receive the target read clock signal and a read data signal sent by the memory, and perform latch processing on the read data signal by using the target read clock signal.

Abstract: A memory, a control apparatus, a clock processing method, and an electronic device are provided. A clock processing circuit in the memory includes: a duty cycle module, configured to adjust a duty cycle of a data clock signal to output an internal clock signal; a first clock generation module, configured to receive the internal clock signal, and output a first read clock signal based on the internal clock signal, the first read clock signal being a pulse signal; a second clock generation module, configured to generate and output a second read clock signal during existence of the first read clock signal, the second read clock signal having only one level state change edge; and a selection module, configured to receive the first read clock signal and the second read clock signal, and output the first read clock signal or the second read clock signal as a target read clock signal.

Abstract: Methods, systems, and devices for debug capabilities of a memory system with a pin are described. An apparatus may include a memory system that includes a plurality of pins of a first type that are configured to communicate information as part of operating the memory system and a pin of a second type. The apparatus may also include a circuit coupled with the memory system, the circuit including a resistor that is coupled with the pin of the second type. The memory system may include a controller that selects a value for the resistor and generates a code as part of a memory management operation to determine one or more operating conditions of the memory system based on selecting the value. The memory system controller may also determine an error associated with the code based on generating the code and the selected value of the resistor.

Abstract: Methods, systems, and devices for configurable memory die capacitance are described. A memory device may include a capacitive component, which may include one or more capacitors and associated switching components. The capacitive component may be coupled with an input/output (I/O) pad and an associated input buffer, and the one or more capacitors of the capacitive component may be selectively couplable with the I/O pad via the switching components. Switching components may be activated individually, in coordination, or not at all, such that one, multiple, or none of the capacitors may be coupled with the I/O pad. The capacitive component, I/O pad, and input buffer may be included in a same die of the memory device. In some cases, a configuration of the capacitive component may be based on signaling received from a host device.

Abstract: Methods, systems, and devices for testing circuit for a memory device are described. An apparatus may include a memory system including contacts that route signals to different regions of the memory system. The apparatus may include a first substrate including a memory system interface coupled with the memory system and a probe interface. The apparatus may also include a second substrate coupled with a host system interface of the first substrate and receive the signal of the memory system from the memory system interface. The first interface may route a signal of the memory system to the probe interface and a tester to determine the signal's integrity and any errors associated with the memory system. The first substrate may include a resistor coupled with the contacts of the memory system, the resistor on a surface of the interface may be configured to improve the signal at the tester.

Abstract: The present invention relates to methods of treating p53 wild type (WT) tumors. In particular, the invention provides novel therapies for p53 WT tumors based on the combination of Mouse Double Minute 2 (MDM2) inhibitors, e.g. HDM201, together with Casein Kinase 1 alpha (CK1?) degrading agents and/or an MDM4 inhibitors, e.g. lenalidomide. The combination may be used in the treatment of solid as well as hematologic p53 WT tumors, e.g. Merkel cell carcinoma (MCC) or myelodysplastic syndrome (MDS).