Patents by Inventor Jingyu Lian

Jingyu Lian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method to produce low leakage high K materials in thin film form
    Publication number: 20040121566
    Abstract: High K dielectric materials having very low leakage current are formed by depositing a thin amorphous layer of a high K dielectric and a crystalline layer of a high K dielectric over the amorphous layer. Semiconductor devices including composite high K dielectric materials, and methods of fabricating such devices, are also disclosed.
    Type: Application
    Filed: December 23, 2002
    Publication date: June 24, 2004
    Applicant: Infineon Technologies North America Corp
    Inventors: Robert Benjamin Laibowitz, Jingyu Lian
  • Recess Pt structure for high k stacked capacitor in DRAM and FRAM, and the method to form this structure
    Patent number: 6596580
    Abstract: The exposure of the interface between the bottom electrode and barrier layer to a high temperature oxygen ambience is avoided by recessed Pt-in-situ deposited with a barrier layer.
    Type: Grant
    Filed: October 18, 2001
    Date of Patent: July 22, 2003
    Assignees: Infineon Technologies AG, International Business Machines Corporation
    Inventors: Jingyu Lian, Greg Costrini, Laertis Economikos, Michael Wise
  • Recess Pt structure for high k stacked capacitor in DRAM and FRAM, and the method to form this structure
    Publication number: 20030077858
    Abstract: The exposure of the interface between the bottom electrode and barrier layer to a high temperature oxygen ambience is avoided by recessed Pt-in-situ deposited with a barrier layer.
    Type: Application
    Filed: October 18, 2001
    Publication date: April 24, 2003
    Inventors: Jingyu Lian, Greg Costrini, Laertis Economikos, Michael Wise
  • Methods for crystallizing metallic oxide dielectric films at low temperature
    Patent number: 6432725
    Abstract: A method for forming a crystalline dielectric layer deposits an amorphous metallic oxide dielectric layer on a surface. The amorphous metallic oxide dielectric layer is treated with a plasma at a temperature of less than or equal to 400 degrees Celsius to form a crystalline layer.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: August 13, 2002
    Assignees: Infineon Technologies AG, International Business Machines Corporation
    Inventors: Jingyu Lian, Kwong Hon Wong, Katherine Saenger, Chenting Lin
  • Multi-layer Pt electrode for DRAM and FRAM with high K dielectric materials
    Publication number: 20020084481
    Abstract: A multi-layer electrode (246) and method of fabrication thereof in which a conductive region (244) is separated from a barrier layer (222) by a first conductive liner (240) and a second conductive liner (242). First conductive layer (240) comprises Pt, and second conductive liner (242) comprises a thin layer of conductive oxide. The multi-layer electrode (246) prevents oxygen diffusion through the top conductive region (244) and reduces material variation during electrode patterning.
    Type: Application
    Filed: December 28, 2000
    Publication date: July 4, 2002
    Inventors: Jingyu Lian, Chenting Lin, Nicolas Nagel, Michael Wise