Patents by Inventor Jin-Ho Chun
Jin-Ho Chun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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LITHIUM COMPOSITE OXIDE AND POSITIVE ELECTRODE ACTIVE MATERIAL FOR SECONDARY BATTERY CONTAINING SAME
Publication number: 20240136510Abstract: A positive electrode active material including a first lithium composite oxide particle including a secondary particle formed by aggregation of one or more primary particles, and a coating oxide occupying at least a part of at least one of surfaces of the secondary particle, grain boundaries between the primary particles, or surfaces of the primary particles, the positive electrode active material satisfying an equation of 1.3?a/b?3.0, wherein a represents a max peak intensity at 2theta=44.75° to 44.80° and b represents a max peak intensity at 2theta=45.3° to 45.6° in X-ray diffraction (XRD) analysis using Cu K? radiation.Type: ApplicationFiled: May 21, 2023Publication date: April 25, 2024Inventors: Yu Gyeong CHUN, Moon Ho CHOI, Yoon Young CHOI, Jong Seung SHIN, Yong Hwan GWON, Jin Ho BAE, Ji Won KIM, Sang Hyeok KIM -
Patent number: 11798906Abstract: A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.Type: GrantFiled: December 15, 2021Date of Patent: October 24, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jeong-gi Jin, Nae-in Lee, Jum-yong Park, Jin-ho Chun, Seong-min Son, Ho-Jin Lee
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Patent number: 11469202Abstract: A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed on a substrate. The redistribution pattern may be formed on the protective layer. An upper surface of the redistribution may be substantially flat. The pad pattern may be formed directly on the redistribution pattern. An upper surface of the pad pattern may be substantially flat. The insulating polymer layer may be formed on the redistribution pattern and the pad pattern. An upper surface of the insulating polymer layer may be lower than the upper surface of the pad pattern.Type: GrantFiled: September 23, 2020Date of Patent: October 11, 2022Inventors: Seong-Min Son, Jeong-Gi Jin, Jin-Ho An, Jin-Ho Chun, Kwang-Jin Moon, Ho-Jin Lee
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Publication number: 20220108962Abstract: A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.Type: ApplicationFiled: December 15, 2021Publication date: April 7, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Jeong-gi JIN, Nae-in LEE, Jum-yong PARK, Jin-ho CHUN, Seong-min SON, Ho-Jin LEE
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Patent number: 11251144Abstract: A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.Type: GrantFiled: October 30, 2019Date of Patent: February 15, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Jeong-gi Jin, Nae-in Lee, Jum-yong Park, Jin-ho Chun, Seong-min Son, Ho-jin Lee
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Publication number: 20210005565Abstract: A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed on a substrate. The redistribution pattern may be formed on the protective layer. An upper surface of the redistribution may be substantially flat. The pad pattern may be formed directly on the redistribution pattern. An upper surface of the pad pattern may be substantially flat. The insulating polymer layer may be formed on the redistribution pattern and the pad pattern. An upper surface of the insulating polymer layer may be lower than the upper surface of the pad pattern. The semiconductor device may have a high reliability.Type: ApplicationFiled: September 23, 2020Publication date: January 7, 2021Inventors: Seong-Min SON, Jeong-Gi JIN, Jin-Ho AN, Jin-Ho CHUN, Kwang-Jin MOON, Ho-Jin LEE
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Patent number: 10833032Abstract: A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed on a substrate. The redistribution pattern may be formed on the protective layer. An upper surface of the redistribution may be substantially flat. The pad pattern may be formed directly on the redistribution pattern. An upper surface of the pad pattern may be substantially flat. The insulating polymer layer may be formed on the redistribution pattern and the pad pattern. An upper surface of the insulating polymer layer may be lower than the upper surface of the pad pattern. The semiconductor device may have a high reliability.Type: GrantFiled: August 1, 2018Date of Patent: November 10, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Seong-Min Son, Jeong-Gi Jin, Jin-Ho An, Jin-Ho Chun, Kwang-Jin Moon, Ho-Jin Lee
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Patent number: 10580726Abstract: A semiconductor device and a method of manufacturing the same, the device including a through-hole electrode structure extending through a substrate; a redistribution layer on the through-hole electrode structure; and a conductive pad, the conductive pad including a penetrating portion extending through the redistribution layer; and a protrusion portion on the penetrating portion, the protrusion portion protruding from an upper surface of the redistribution layer, wherein a central region of an upper surface of the protrusion portion is flat and not closer to the substrate than an edge region of the upper surface of the protrusion portion.Type: GrantFiled: August 21, 2018Date of Patent: March 3, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jin-Ho Chun, Seong-Min Son, Hyung-Jun Jeon, Kwang-Jin Moon, Jin-Ho An, Ho-Jin Lee, Atsushi Fujisaki
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Publication number: 20200066666Abstract: A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.Type: ApplicationFiled: October 30, 2019Publication date: February 27, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Jeong-gi Jin, Nae-in Lee, Jum-yong Park, Jin-ho Chun, Seong-min Son, Ho-jin Lee
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Patent number: 10483224Abstract: A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.Type: GrantFiled: October 24, 2017Date of Patent: November 19, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Jeong-gi Jin, Nae-in Lee, Jum-yong Park, Jin-ho Chun, Seong-min Son, Ho-jin Lee
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Publication number: 20190131228Abstract: A semiconductor device and a method of manufacturing the same, the device including a through-hole electrode structure extending through a substrate; a redistribution layer on the through-hole electrode structure; and a conductive pad, the conductive pad including a penetrating portion extending through the redistribution layer; and a protrusion portion on the penetrating portion, the protrusion portion protruding from an upper surface of the redistribution layer, wherein a central region of an upper surface of the protrusion portion is flat and not closer to the substrate than an edge region of the upper surface of the protrusion portion.Type: ApplicationFiled: August 21, 2018Publication date: May 2, 2019Inventors: Jin-Ho CHUN, Seong-Min SON, Hyung-Jun JEON, Kwang-Jin MOON, Jin-Ho AN, Ho-Jin LEE, Atsushi FUJISAKI
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Publication number: 20190067228Abstract: A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed on a substrate. The redistribution pattern may be formed on the protective layer. An upper surface of the redistribution may be substantially flat. The pad pattern may be formed directly on the redistribution pattern. An upper surface of the pad pattern may be substantially flat. The insulating polymer layer may be formed on the redistribution pattern and the pad pattern. An upper surface of the insulating polymer layer may be lower than the upper surface of the pad pattern. The semiconductor device may have a high reliability.Type: ApplicationFiled: August 1, 2018Publication date: February 28, 2019Inventors: Seong-Min SON, Jeong-Gi JIN, Jin-Ho AN, Jin-Ho CHUN, Kwang-Jin MOON, Ho-Jin LEE
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Publication number: 20180138137Abstract: A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.Type: ApplicationFiled: October 24, 2017Publication date: May 17, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Jeong-gi JIN, Nae-in Lee, Jum-yong Park, Jin-ho Chun, Seong-min Son, Ho-jin Lee
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Publication number: 20170345713Abstract: A semiconductor chip including through silicon vias (TSVs), wherein the TSVs may be prevented from bending and the method of fabricating the semiconductor chip may be simplified, and a method of fabricating the semiconductor chip. The semiconductor chip includes a silicon substrate having a first surface and a second surface; a plurality of TSVs which penetrate the silicon substrate and protrude above the second surface of the silicon substrate; a polymer pattern layer which is formed on the second surface of the silicon substrate, surrounds side surfaces of the protruding portion of each of the TSVs, and comprises a flat first portion and a second portion protruding above the first portion; and a plated pad which is formed on the polymer pattern layer and covers a portion of each of the TSVs exposed from the polymer pattern layer.Type: ApplicationFiled: June 30, 2017Publication date: November 30, 2017Inventors: Jin-ho Chun, Byung-lyul PARK, Hyun-soo CHUNG, Gil-heyun CHOI, Son-kwan HWANG
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Patent number: 9698051Abstract: A semiconductor chip including through silicon vias (TSVs), wherein the TSVs may be prevented from bending and the method of fabricating the semiconductor chip may be simplified, and a method of fabricating the semiconductor chip. The semiconductor chip includes a silicon substrate having a first surface and a second surface; a plurality of TSVs which penetrate the silicon substrate and protrude above the second surface of the silicon substrate; a polymer pattern layer which is formed on the second surface of the silicon substrate, surrounds side surfaces of the protruding portion of each of the TSVs, and comprises a flat first portion and a second portion protruding above the first portion; and a plated pad which is formed on the polymer pattern layer and covers a portion of each of the TSVs exposed from the polymer pattern layer.Type: GrantFiled: January 6, 2015Date of Patent: July 4, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-ho Chun, Byung-Iyul Park, Hyun-soo Chung, Gil-heyun Choi, Son-kwan Hwang
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Patent number: 9691685Abstract: A semiconductor device includes a substrate having a die region and a scribe region surrounding the die region, a plurality of via structures penetrating through the substrate in the die region, a portion of the via structure being exposed over a surface of the substrate, and a protection layer pattern structure provided on the surface of the substrate surrounding a sidewall of the exposed portion of the via structure and having a protruding portion covering at least a portion of the scribe region adjacent to the via structure.Type: GrantFiled: May 25, 2016Date of Patent: June 27, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyu-Ha Lee, Hyung-Jun Jeon, Jum-Yong Park, Byung-Lyul Park, Ji-Soon Park, Jin-Ho An, Jin-Ho Chun
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Publication number: 20170125364Abstract: An integrated circuit device can include a first Through Via (TV) region including first TV structures that are spaced apart from one another at a first pitch in first and second directions. A second TV region can include second TV structures that are spaced apart from one another at the first pitch in the first and second directions. A TV free region can separate directly adjacent first and second TV structures from one another by a spacing distance measured in the first or second direction that is greater than the first pitch and an alignment key can be defined as a geometric pattern including one of the second TV structures and the TV free region.Type: ApplicationFiled: August 30, 2016Publication date: May 4, 2017Inventors: Jung-Hyun Cho, Kwang-Ho Ryu, Ji-Hye Shin, Jin-Ho Chun
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Publication number: 20170033032Abstract: A semiconductor device includes a substrate having a die region and a scribe region surrounding the die region, a plurality of via structures penetrating through the substrate in the die region, a portion of the via structure being exposed over a surface of the substrate, and a protection layer pattern structure provided on the surface of the substrate surrounding a sidewall of the exposed portion of the via structure and having a protruding portion covering at least a portion of the scribe region adjacent to the via structure.Type: ApplicationFiled: May 25, 2016Publication date: February 2, 2017Inventors: Kyu-Ha Lee, Hyung-Jun Jeon, Jum-Yong Park, Byung-Lyul Park, Ji-Soon Park, Jin-Ho An, Jin-Ho Chun
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Patent number: 9520361Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate, a first conductive structure on the substrate, and a second conductive structure on the first conductive structure. The semiconductor device includes first and second metal-diffusion-blocking layers on respective sidewalls of the first and second conductive structures. The semiconductor device includes an insulating layer between the first and second metal-diffusion-blocking layers. Moreover, the semiconductor device includes a metal-diffusion-shield pattern in the insulating layer and spaced apart from the first conductive structure.Type: GrantFiled: November 10, 2015Date of Patent: December 13, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Pil-Kyu Kang, Seok-Ho Kim, Tae-Yeong Kim, Hyo-Ju Kim, Byung-Lyul Park, Joo-Hee Jang, Jin-Ho Chun
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Patent number: 9461007Abstract: A wafer-to-wafer bonding structure may include: a first wafer including a first insulating layer on a first substrate and on a first copper (Cu) pad that penetrates the first insulating layer and has portions protruding from an upper surface of the first insulating layer, and a first barrier metal layer on a lower surface and sides of the first Cu pad; a second wafer including a second insulating layer on a second substrate and on a second copper (Cu) pad that penetrates the second insulating layer, has portions protruding from an upper surface of the second insulating layer, and is bonded to the first Cu pad, and a second barrier metal layer on a lower surface and sides of the second Cu pad; and a polymer layer covering protruding sides of the first and second barrier metal layers and disposed between the first and second wafers.Type: GrantFiled: July 10, 2015Date of Patent: October 4, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-ho Chun, Pil-kyu Kang, Byung-lyul Park, Jae-hwa Park, Ju-il Choi