Abstract: A winder for an electrode assembly of a rechargeable battery for improving space usage is disclosed. The winder includes a plurality of spools supplying a negative electrode member, a positive electrode member, a first separator member, and a second separator member, a mandrel stacking and spirally winding the first separator member, the negative electrode member, the second separator member, and the positive electrode member supplied by the spool, a first frame accommodating a predetermined number of spools from among the plurality of spools and the mandrel, a second frame connected to the first frame and accommodating other spools from among the plurality of spools, a reorienter installed between the first frame and the second frame and reorienting a progressing direction of one of the members, and a position controller controlling a position of the member that passes through the reorienter and progresses towards the mandrel.

Abstract: Disclosed is a winder for an electrode assembly of a rechargeable battery for improving space usage. The winder includes a plurality of spools supplying a negative electrode member, a positive electrode member, a first separator member, and a second separator member, a mandrel stacking and spirally winding the first separator member, the negative electrode member, the second separator member, and the positive electrode member supplied by the spool, a first frame accommodating a predetermined number of spools from among the plurality of spools and the mandrel, a second frame connected to the first frame and accommodating other spools from among the plurality of spools, a reorienter installed between the first frame and the second frame and reorienting a progressing direction of one of the members, and a position controller controlling a position of the member that passes through the reorienter and progresses towards the mandrel.

Abstract: A probe card to connect a semiconductor device to test equipment includes a Printed Circuit Board (PCB) in which an electrical wiring pattern is formed, a first connector fixed on an upper surface of the PCB to connect the test equipment to the PCB, probe needles connected to electrode pads of the semiconductor device, and a Flexible PCB (FPCB) to connect the PCB to the probe needles. Accordingly, a signal transmission characteristic can be enhanced, test expenses can be reduced, and ground noise can be reduced.

Abstract: A probe card to connect a semiconductor device to test equipment includes a Printed Circuit Board (PCB) in which an electrical wiring pattern is formed, a first connector fixed on an upper surface of the PCB to connect the test equipment to the PCB, probe needles connected to electrode pads of the semiconductor device, and a Flexible PCB (FPCB) to connect the PCB to the probe needles. Accordingly, a signal transmission characteristic can be enhanced, test expenses can be reduced, and ground noise can be reduced.

Abstract: A probe card to connect a semiconductor device to test equipment includes a Printed Circuit Board (PCB) in which an electrical wiring pattern is formed, a first connector fixed on an upper surface of the PCB to connect the test equipment to the PCB, probe needles connected to electrode pads of the semiconductor device, and a Flexible PCB (FPCB) to connect the PCB to the probe needles. Accordingly, a signal transmission characteristic can be enhanced, test expenses can be reduced, and ground noise can be reduced.

Abstract: Memory modules and methods of testing memory modules are provided that include at least one memory device responsive to a memory clock signal having a memory clock frequency and a data buffer. The data buffer is responsive to a buffer clock signal having a first buffer clock frequency that is different from the memory clock frequency during a normal mode of operation and having a second buffer clock frequency that is equal to the memory clock frequency during a test mode of operation.

Abstract: An electronic system having a plurality of dynamic semiconductor memory devices and a refresh method for the same. The system comprises a plurality of dynamic semiconductor memory devices and a controller. Each of the dynamic semiconductor memory devices includes a storage device for storing a designated number designating an order for performing a refresh operation, a refresh enable signal generating circuit for generating a refresh enable signal in response to a refresh control command supplied from the controller and a delaying circuit for delaying the refresh enable signal by different time intervals determined by the designated number.

Abstract: An integrated circuit device includes a delay circuit that is configured to delay a clock signal and is further configured to generate an output data signal in response to the delayed clock signal and an input data signal. Multiple devices are configured to respectively receive the output data signal in response to the clock signal.

Abstract: An electronic system having a plurality of dynamic semiconductor memory devices and a refresh method for the same. The system comprises a plurality of dynamic semiconductor memory devices and a controller. Each of the dynamic semiconductor memory devices includes a storage device for storing a designated number designating an order for performing a refresh operation, a refresh enable signal generating circuit for generating a refresh enable signal in response to a refresh control command supplied from the controller and a delaying circuit for delaying the refresh enable signal by different time intervals determined by the designated number.

Abstract: Memory modules and methods of testing memory modules are provided that include at least one memory device responsive to a memory clock signal having a memory clock frequency and a data buffer. The data buffer is responsive to a buffer clock signal having a first buffer clock frequency that is different from the memory clock frequency during a normal mode of operation and having a second buffer clock frequency that is equal to the memory clock frequency during a test mode of operation.

Abstract: An integrated circuit device includes a delay circuit that is configured to delay a clock signal and is further configured to generate an output data signal in response to the delayed clock signal and an input data signal. Multiple devices are configured to respectively receive the output data signal in response to the clock signal.

Abstract: A semiconductor memory device is disclosed that programmably varies an output pin transmitting output data from a comparator during a test mode. Also disclosed is a read method for the test mode. The semiconductor memory device includes a comparator that compares a plurality of output data read from the memory cell array and an output pin determining unit that programmably varies a pin transmitting an output of the comparator during the test mode. Thus, when multiple semiconductor memory devices are installed in a single memory module, the output pins of the semiconductor memory devices are variously determined using the output pin determining unit so that data can be simultaneously read from more than one semiconductor memory device at a time during a test of a memory module, to thereby reduce the module test time.

Abstract: A high-speed disturb testing method for a semiconductor memory device is disclosed, includes the steps of: (a) writing first piece of data in all of the memory cells in the memory cell array; (b) reading and confirming the first piece data written in each memory cell of the memory cell array; (c) writing second piece data in all of the memory cells connected to the plurality of disturb word lines; (d) reading and confirming the second piece data from all of the memory cells (e) fixing the mode of the disturb word line to the test mode; (f) repeatedly writing the second piece data in all of the memory cells connected to the plurality of disturb word lines; (g) changing the test mode to the normal mode; (h) refreshing all of the memory cells; (i) reading and confirming the first piece data from a word line located close to the selected plurality of disturb word lines; (j) writing the first piece data in all of memory cells connected to the plurality of disturb word lines; (k) repeating the steps (3) to (10), to