Abstract: A system on a chip may include a codec module configured to receive an image including a plurality of first pixel data and output a plurality of second pixel data through a system bus. The codec module comprises at least one (M+N) bit logic circuit including M bit logic and N bit logic. The codec module is configured to operate in a first mode where the (M+N) bit logic circuit performs a dithering operation on the first pixel data of (M+N) bits and generates the second pixel data including at least M bits. The codec module is configured to operate in a second mode where the M-bit logic selectively operates and outputs the second pixel data of M bits.

Abstract: An image processor is provided. In some examples, the image processor is in a system on chip or part of a larger image processing system. The image processor may include an application processor, a codec module, and a memory controller, and in some examples may also function with a dithering unit, a display controller, a display, and/or a CMOS image sensor. The image processor processes, stores, and reads image data using an embedded memory and/or an external memory. The image data is comprised of a plurality of pixels, each of which may include a first and second set of bits that can be separately or simultaneously accessed at the memory in a first and second region of the memory using one or more addresses. The first set of bits may correspond to the more significant bits of each pixel and the second set of bits may correspond to the less significant bits.

Abstract: An image processing system comprises a first image processing device configured to process a frame of image data comprising a plurality of pixels, each having corresponding pixel values. Each of the pixel values include a first and second set of bits that may be separately or simultaneously accessed and/or processed. The first set of bits may correspond to the more significant bits of each pixel and the second set of bits may correspond to the less significant bits. In some examples the number of bits in each of the first and second set of bits may correspond to the width of a used data bus and/or features of a peripheral device connected to the image processor, such as a display.

Abstract: An image processor is provided. In some examples, the image processor is in a system on chip or part of a larger image processing system. The image processor may include an application processor, a codec module, and a memory controller, and in some examples may also function with a dithering unit, a display controller, a display, and/or a CMOS image sensor. The image processor processes, stores, and reads image data using an embedded memory and/or an external memory. The image data is comprised of a plurality of pixels, each of which may include a first and second set of bits that can be separately or simultaneously accessed at the memory in a first and second region of the memory using one or more addresses. The first set of bits may correspond to the more significant bits of each pixel and the second set of bits may correspond to the less significant bits.

Abstract: A method of processing image data comprises processing a frame of image data comprising a plurality of pixels, each having corresponding pixel values. Each of the pixel values include a first and second set of bits that may be separately or simultaneously accessed and/or processed. The first set of bits may correspond to the more significant bits of each pixel and the second set of bits may correspond to the less significant bits. In some examples the number of bits in each of the first and second set of bits may correspond to the width of a used data bus and/or features of a peripheral device connected to the image processor, such as a display.

Abstract: An image processor is provided. In some examples, the image processor is in a system on chip or part of a larger image processing system. The image processor may include an application processor, a codec module, and a memory controller, and in some examples may also function with a dithering unit, a display controller, a display, and/or a CMOS image sensor. The image processor processes, stores, and reads image data using an embedded memory and/or an external memory. The image data is comprised of a plurality of pixels, each of which may include a first and second set of bits that can be separately or simultaneously accessed at the memory in a first and second region of the memory using one or more addresses. The first set of bits may correspond to the more significant bits of each pixel and the second set of bits may correspond to the less significant bits.

Abstract: An image processor processes a plurality of pixels. Each of the pixels include a first and second set of bits that can be separately or simultaneously in first and second regions of a memory using one or more addresses. The first set of bits may correspond to the more significant bits of each pixel and the second set of bits may correspond to the less significant bits. In some examples the number of bits in each of the first and second set of bits may be selected according to the width of a used data bus and/or features of a peripheral device connected to the image processor such as a display.

Abstract: An image processor is provided. In some examples, the image processor is in a system on chip or part of a larger image processing system. The image processor may include an application processor, a codec module, and a memory controller, and in some examples may also function with a dithering unit, a display controller, a display, and/or a CMOS image sensor. The image processor processes, stores, and reads image data using an embedded memory and/or an external memory. The image data is comprised of a plurality of pixels, each of which may include a first and second set of bits that can be separately or simultaneously accessed at the memory in a first and second region of the memory using one or more addresses. The first set of bits may correspond to the more significant bits of each pixel and the second set of bits may correspond to the less significant bits.

Abstract: A bit stream processing device may include a virtual division memory, a stream shift buffer, a decoder circuit, and a controller. The virtual division memory may be divided into a plurality of group memory regions configured to store a plurality of stream groups in the respective group memory regions and to output a memory bit stream. The stream groups may be included in an input bit stream. The stream shift buffer is configured to receive and store the memory bit stream and output a buffer bit stream. The decoder circuit is configured to perform a decoding operation on the buffer bit stream from the stream shift buffer. The controller is configured to control operations of the virtual division memory, the stream shift buffer, and the decoder circuit.

Abstract: A bit stream processing device may include a virtual division memory, a stream shift buffer, a decoder circuit, and a controller. The virtual division memory may be divided into a plurality of group memory regions configured to store a plurality of stream groups in the respective group memory regions and to output a memory bit stream. The stream groups may be included in an input bit stream. The stream shift buffer is configured to receive and store the memory bit stream and output a buffer bit stream. The decoder circuit is configured to perform a decoding operation on the buffer bit stream from the stream shift buffer. The controller is configured to control operations of the virtual division memory, the stream shift buffer, and the decoder circuit.

Abstract: The present invention relates to a PID/section filter which is adapted without any restriction to an ATSC standard or a DVB standard, comprising a processor module for detecting a PID and a TID by decoding the input transport stream, downloading the information requested by the viewer, and controlling the operation of the each system unit in order to store the information on a memory or ignores it, a PID comparing circuit module for comparing the PID value stored on an internal register with the PID value from the processor module, a download circuit module for downloading the extracted information among the decoded information by the processor module, and an external memory managing module for storing the information extracted in-accordance with the request of the viewer among the information decoded on the processor module.

Abstract: The present invention relates to a PID/section filter which is adapted without any restriction to an ATSC standard or a DVB standard, comprising a processor module for detecting a PID and a TID by decoding the input transport stream, downloading the information requested by the viewer, and controlling the operation of the each system unit in order to store the information on a memory or ignores it, a PID comparing circuit module for comparing the PID value stored on an internal register with the PID value from the processor module, a download circuit module for downloading the extracted information among the decoded information by the processor module, and an external memory managing module for storing the information extracted in-accordance with the request of the viewer among the information decoded on the processor module.