Abstract: An integrated circuit device including an active region; an active cutting region at a side of the active region in a first direction; a fin active pattern extending on the active region in the first direction, the fin active pattern including a source region and a drain region; a gate pattern extending across the active region and the fin active pattern in a second direction perpendicular to the first direction, the gate pattern not being in the active cutting region; and an isolated gate contact region in contact with the gate pattern outside of the active region.

Abstract: A semiconductor device is tested by disposing an antenna-in-package (AiP) module under a test antenna. A first signal is transmitted with a first antenna of the AiP module. The test antenna is moved to a power output peak of the first signal. A second signal is transmitted with a second antenna of the AiP module. The test antenna is moved along a first directional axis from the power output peak of the first signal to a power output peak of the second signal while a second directional axis of the test antenna is held static. The first antenna of the AiP module is tested while the test antenna is at the power output peak of the first signal. The second antenna of the AiP module is tested while the test antenna is at the power output peak of the second signal.

Abstract: A semiconductor device is tested by disposing an antenna-in-package (AiP) module under a test antenna. A first signal is transmitted with a first antenna of the AiP module. The test antenna is moved to a power output peak of the first signal. A second signal is transmitted with a second antenna of the AiP module. The test antenna is moved along a first directional axis from the power output peak of the first signal to a power output peak of the second signal while a second directional axis of the test antenna is held static. The first antenna of the AiP module is tested while the test antenna is at the power output peak of the first signal. The second antenna of the AiP module is tested while the test antenna is at the power output peak of the second signal.

Abstract: An integrated circuit device including an active region; an active cutting region at a side of the active region in a first direction; a fin active pattern extending on the active region in the first direction, the fin active pattern including a source region and a drain region; a gate pattern extending across the active region and the fin active pattern in a second direction perpendicular to the first direction, the gate pattern not being in the active cutting region; and an isolated gate contact region in contact with the gate pattern outside of the active region.

Abstract: An integrated circuit device including an active region; an active cutting region at a side of the active region in a first direction; a fin active pattern extending on the active region in the first direction, the fin active pattern including a source region and a drain region; a gate pattern extending across the active region and the fin active pattern in a second direction perpendicular to the first direction, the gate pattern not being in the active cutting region; and an isolated gate contact region in contact with the gate pattern outside of the active region.

Abstract: An integrated circuit device including an active region; an active cutting region at a side of the active region in a first direction; a fin active pattern extending on the active region in the first direction, the fin active pattern including a source region and a drain region; a gate pattern extending across the active region and the fin active pattern in a second direction perpendicular to the first direction, the gate pattern not being in the active cutting region; and an isolated gate contact region in contact with the gate pattern outside of the active region.