Abstract: A method for fabricating a semiconductor device includes steps as follows. A gate structure is formed on a substrate. A fluorine-containing dopant is implanted into the substrate to form two lightly doped drain regions at two sides of the gate structure. A thermal treatment process is performed, in which a part of fluorine atoms of the fluorine-containing dopant diffuse onto a surface of the substrate. The part of fluorine atoms are removed.

Abstract: The present invention uses the thinned second pad oxide layer as the pad oxide layer for the subsequent shallow trench isolation process. Therefore, it is not necessary to remove the entire pad oxide layer on the substrate surface after the P-type high-voltage ion well thermal drive-in process. The subsequent step of re-growing the pad oxide layer is omitted, thereby simplifying the process complexity.

Abstract: A resistive random access memory includes a first dielectric layer, a bottom electrode on the first dielectric layer, a variable-resistance layer on the bottom electrode and having a U-shaped cross-sectional profile, a top electrode on the variable-resistance layer and filling a recess in the variable-resistance layer, a second dielectric layer on the first dielectric layer and around the variable-resistance layer and the bottom electrode, and a spacer on the bottom electrode and inserting between the variable-resistance layer and the second dielectric layer.

Abstract: A method for fabricating a semiconductor device is disclosed. A substrate having thereon at least one metal-oxide-semiconductor (MOS) transistor is provided. A stress memorization technique (SMT) process is performed. The SMT process includes steps of depositing an SMT film covering the at least one MOS transistor on the substrate, and subjecting the SMT film to a thermal process. A lithographic process and an etching process are performed to form a patterned SMT film. A silicide layer is formed on the MOS transistor. The patterned SMT film acts as a salicide block layer when forming the silicide layer.

Abstract: The invention provides a method for manufacturing a semiconductor structure, which comprises the following steps: a high voltage metal oxide semiconductor (HVMOS) is provided, the high voltage metal oxide semiconductor comprises a substrate, and the substrate comprises an NMOS region and a PMOS region, the NMOS region and the PMOS region each comprise an oxide layer, a P-type ion doping step on the PMOS region is performed, the thickness of the oxide layer of the PMOS region is reduced during the P-type ion doping step, and an N-type ion doping step is then performed on the NMOS region after the P-type ion doping step, the thickness of the oxide layer of the NMOS region is reduced during the N-type ion doping step.

Abstract: The present invention provides a semiconductor device and a method of fabricating the same, which includes a substrate, a gate structure, and a dielectric layer. The gate structure is disposed on the substrate and includes an inverted trapezoidal shape. The dielectric layer is disposed on the substrate, and the gate structure is disposed within the dielectric layer. The gate structure includes a metal gate structure or a polysilicon gate structure.

Abstract: The present disclosure provides a testkey structure and a monitoring method with a testkey structure, and the testkey structure includes a first diffusion region and a second diffusion region, a first gate and a second gate, a first epitaxial layer and a second epitaxial layer, and an input pad and an output pad. The first diffusion region and the second diffusion region are disposed in a substrate. The first gate and the second gate are disposed on a substrate, across the first diffusion region and the second diffusion region respectively. The first epitaxial layer and the second epitaxial layer are respectively disposed on the second diffusion region and the first diffusion region, separately disposed between the first gate and the second gate. The input pad and the output pad are electrically connected to the first epitaxial layer and the second epitaxial layer respectively.

Abstract: A method for fabricating a semiconductor device is disclosed. A substrate having thereon at least one metal-oxide-semiconductor (MOS) transistor is provided. A stress memorization technique (SMT) process is performed. The SMT process includes steps of depositing an SMT film covering the at least one MOS transistor on the substrate, and subjecting the SMT film to a thermal process. A lithographic process and an etching process are performed to form a patterned SMT film. A silicide layer is formed on the MOS transistor. The patterned SMT film acts as a salicide block layer when forming the silicide layer.

Abstract: A resistive random access memory includes a first dielectric layer, a bottom electrode on the first dielectric layer, a variable-resistance layer on the bottom electrode and having a U-shaped cross-sectional profile, a top electrode on the variable-resistance layer and filling a recess in the variable-resistance layer, a second dielectric layer on the first dielectric layer and around the variable-resistance layer and the bottom electrode, and a spacer on the bottom electrode and inserting between the variable-resistance layer and the second dielectric layer.

Abstract: A resistive random access memory includes a bottom electrode, a variable-resistance layer on the bottom electrode and having a U-shaped cross-sectional profile, and a top electrode on the variable-resistance layer and filling a recess in the variable-resistance layer.

Abstract: The invention provides a semiconductor testkey, which comprises a testkey on a substrate, the testkey comprises a first resistor pattern, a second resistor pattern and a third resistor pattern arranged in a strip, the distance between the first resistor pattern and the second resistor pattern is defined as a first distance, and the distance between the second resistor pattern and the third resistor pattern is defined as a second distance, the first resistor pattern, the second resistor pattern and the third resistor pattern have the same pattern, and the second distance is larger than the first distance.

Abstract: The invention provides a semiconductor testkey pattern, the semiconductor testkey pattern includes a high density device region and a plurality of resistor pairs surrounding the high density device region, wherein each resistor pair includes two mutually symmetrical resistor patterns.

Abstract: A resistive random access memory includes a bottom electrode, a variable-resistance layer on the bottom electrode and having a U-shaped cross-sectional profile, and a top electrode on the variable-resistance layer and filling a recess in the variable-resistance layer.

Abstract: The invention provides a semiconductor testkey pattern, the semiconductor testkey pattern includes a high density device region and a plurality of resistor pairs surrounding the high density device region, wherein each resistor pair includes two mutually symmetrical resistor patterns.

Abstract: A radiofrequency device includes a semiconductor substrate, an inductor structure, a shielding structure, and a mask pattern. The semiconductor substrate includes a first region and a second region. The inductor structure is disposed on the first region of the semiconductor substrate. The shielding structure is disposed on the first region of the semiconductor substrate and located between the inductor structure and the semiconductor substrate in a vertical direction. The mask pattern is disposed on the semiconductor substrate. A first portion of the mask pattern is disposed on the shielding structure and directly contacts the shielding structure, and a top surface of the shielding structure is completely covered by the first portion of the mask pattern.

Abstract: A method for forming a semiconductor device is disclosed. A semiconductor substrate having thereon an NMOS region, a PMOS region, and a non-silicide region is provided. An NMOS transistor is formed within the NMOS region and a PMOS transistor is formed within the PMOS region. A stress memorization technique (SMT) layer covering the NMOS region, the PMOS region, and the non-silicide region is formed. The SMT layer is removed from the PMOS region. A stress is transferred from the SMT layer into an N-channel of the NMOS transistor. The SMT layer is removed from the NMOS region, while leaving the SMT layer in the non-silicide region intact. A self-aligned silicidation (SAC) process is performed to form a salicide layer in the NMOS region and the PMOS region.

Abstract: An RRAM structure includes a substrate. An RRAM is embedded in the substrate. The RRAM includes a bottom electrode, a metal oxide layer and a top electrode. A first doped region is embedded in the substrate and surrounds the bottom electrode. A transistor is disposed on the substrate and at one side of the RRAM. The transistor includes a gate structure on the substrate. A source is disposed in the substrate and at one side of the gate structure. A drain is disposed in the substrate and at another side of the gate structure. The first doped region contacts the drain.

Abstract: An RRAM structure includes a substrate. An RRAM is embedded in the substrate. The RRAM includes a bottom electrode, a metal oxide layer and a top electrode. A first doped region is embedded in the substrate and surrounds the bottom electrode. A transistor is disposed on the substrate and at one side of the RRAM. The transistor includes a gate structure on the substrate. A source is disposed in the substrate and at one side of the gate structure. A drain is disposed in the substrate and at another side of the gate structure. The first doped region contacts the drain.