Patents by Inventor Jinjin CHEN

Jinjin CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210256930
    Abstract: The present disclosure provides a gate drive circuit, an array substrate, and a display device. The gate drive circuit includes cascaded shift registers, control circuits, level shifters, voltage stabilization circuits, and first exchanging circuits. The shift registers at respective stages output respective first signals. Each control circuit is configured to process the respective first signal to generate a respective second signal. Each level shifter is configured to convert the voltage level of the respective second signal to generate a respective third signal. Each voltage stabilization circuit is configured to stabilize the respective third signal. The stabilized third signal is outputted as a fourth signal. The first exchanging circuit is configured to enable any of the following: exchanging the first signals at two adjacent stages, exchanging the second signals at two adjacent stages, exchanging the third signals at two adjacent stages, and exchanging the fourth signals at two adjacent stages.
    Type: Application
    Filed: April 1, 2019
    Publication date: August 19, 2021
    Inventors: Shuai CHEN, Xiuzhu TANG, Zhi ZHANG, Xuebo LIANG, Lijun XIONG, Qiyuan WEI, Qi LI, Meiling TAN, Jinjin CHEN, Huan WANG
  • Publication number: 20210233469
    Abstract: Provided are a pixel driving circuit, a pixel driving method and a display panel. The pixel driving circuit includes: a driving circuit, a light emitting circuit, a storage circuit, a reset circuit, a light emitting control circuit and a writing compensation circuit; a first electrode of the storage circuit is coupled to a first node, a second electrode of the storage circuit is coupled to a second node; the reset circuit adjusts voltages of the first node and the second node; the writing compensation circuit writes a data signal of a data line terminal and a compensation data into the driving circuit through an adjustment of the storage circuit; the light emitting control circuit writes a display current, a magnitude of which is related only to the data signal and a voltage of the first voltage terminal, to the light emitting circuit by controlling the driving circuit.
    Type: Application
    Filed: April 8, 2020
    Publication date: July 29, 2021
    Inventors: Shuai CHEN, Xiuzhu TANG, Jianfeng YUAN, Hailong WU, Xing DONG, Zhenguo TIAN, Lijun XIONG, Xuebo LIANG, Xiaoke ZHOU, Jinjin CHEN, Tongguo MA
  • Patent number: 9065764
    Abstract: The present invention discloses a method for maintaining quality of service QoS, which includes: identifying a CLP and a service type of a newly received ATM cell, and obtaining a corresponding QoS label; when the QoS label corresponding to the newly received ATM cell is different from a QoS label corresponding to a buffered ATM cell, encapsulating the buffered ATM cell into a pseudo wire PW packet in a concatenation manner and sending the pseudo wire PW packet, where the QoS label corresponding to the buffered ATM cell is used as a QoS label of a PSN transport header of the PW packet, or is used as QoS labels of both the PSN transport header and a PW header of the PW packet, and buffering the newly received ATM cell. The present invention further provides a corresponding provider edge PE device and a corresponding ATM PWE3 system.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: June 23, 2015
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Haitao Hu, Jinjin Chen, Zhiyong Yan
  • Publication number: 20130315245
    Abstract: The present invention discloses a method for maintaining quality of service QoS, which includes: identifying a CLP and a service type of a newly received ATM cell, and obtaining a corresponding QoS label; when the QoS label corresponding to the newly received ATM cell is different from a QoS label corresponding to a buffered ATM cell, encapsulating the buffered ATM cell into a pseudo wire PW packet in a concatenation manner and sending the pseudo wire PW packet, where the QoS label corresponding to the buffered ATM cell is used as a QoS label of a PSN transport header of the PW packet, or is used as QoS labels of both the PSN transport header and a PW header of the PW packet, and buffering the newly received ATM cell. The present invention further provides a corresponding provider edge PE device and a corresponding ATM PWE3 system.
    Type: Application
    Filed: July 24, 2013
    Publication date: November 28, 2013
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Haitao HU, Jinjin CHEN, Zhiyong YAN