Abstract: A display panel including a pixel circuit and a light-emitting element, the pixel circuit including a driving transistor, a data writing transistor, a threshold compensation transistor, a first reset transistor, a bias transistor, and a light-emitting control module, the data writing transistor being electrically connected to a first terminal of the driving transistor, the threshold compensation transistor being connected in series between a gate of the driving transistor and a second terminal of the driving transistor, and configured to detect and self-compensate a threshold voltage deviation of the driving transistor, the first reset transistor and the bias transistor being electrically connected to the second terminal of the driving transistor, the light-emitting control module being connected in series with the driving transistor and the light-emitting element to control whether a driving current flows through the light-emitting element, the data writing transistor and the first reset transistor having th

Abstract: Provided are a display panel and a display device. The display panel includes a display region and a non-display region. The display region surrounds at least part of the non-display region. The non-display region includes an element disposition region and a bank disposition region surrounding at least part of the element disposition region. The bank disposition region is provided with a bank. The display panel includes a substrate, the bank is disposed on a side of the substrate; a light-emitting layer located on a side of the bank facing away from the substrate and including a first light-emitting portion located in the bank disposition region; and a first light-shielding structure located in the bank disposition region and on a side of the first light-emitting portion facing the substrate. The first light-emitting portion and the first light-shielding structure at least partially overlap along the thickness direction of the display panel.

Abstract: A storage device, infrastructure, and associated method for managing request queue to reduce read tail latencies. A disclosed storage device is disclosed that includes: a set of flash memory chips; and a controller that schedules request from a host using a set of request queues, wherein the controller includes a queue manager that: reorders high priority read requests over low priority write requests in each request queue; suspends low priority write requests to process high priority read requests; and limits a number of low priority write requests allowed in each request queue to a threshold value smaller than a size of each request queue.

Abstract: A method for storing data on a storage device includes receiving data to be stored and a logical address for storing the data. A physical address is determined and the data to be stored is stored at the determined physical address. A table that associates logical addresses with physical addresses is examined to determine a difference relationship between the determined physical address and a corresponding physical address for one of other logical addresses. Information representing the determined physical address is stored in the table, in association with the received logical address, as a function of the determined difference relationship. A data storage device includes controller circuitry and memory for storing a lookup table that associates logical addresses with physical addresses. The controller circuitry operates in accordance with the method.

Abstract: Aspects of the disclosure provide a circuit that includes a memory circuit and a controller circuit. The memory circuit is to have a look-up table (LUT) that associates logical address used in computation with physical address used in storage space. The LUT includes a first level LUT with first level entries corresponding to logical addresses, each first level entry includes an indicator field and a content field, and the indicator field is indicative of a compressible/non-compressible attribute of a physical address associated with a logical address. The controller circuit is to receive a logical address, and translate the logical address into a physical address associated with the logical address based on the LUT.

Abstract: A memory channel command interface for one or more memory channels includes, for each memory channel, programmable storage for memory commands, a single channel processor for executing the memory commands, and a task engine for communicating output of the single channel processor to a memory medium. The memory commands may be organized into jobs including operations that include tasks. The tasks may be stored as part of operations in an operation memory, or may be stored in a task memory with pointers to the tasks being stored as part of operations in the operation memory. The memory channel command interface may further include a memory medium status storage that stores a priority indication for a memory command, based on a condition other than order of arrival or receipt of the memory command, and the single channel processor controls order of execution of memory commands based on the priority indication.

Abstract: A storage drive including first, second, third, fourth and fifth modules. The first module is configured to control transfer of blocks of data between a host device and the storage drive. The second module is configured to transfer the blocks of data to and from a non-volatile semiconductor memory in the storage drive. The third module is configured to generate a first descriptor, which describes a transfer of blocks of data between the second module and the non-volatile semiconductor memory. The fourth module is configured to, according to the first descriptor, generate second descriptors. Each of the second descriptors corresponds to a respective one of the blocks of data. The fifth module is configured to generate instruction signals based on the second descriptors. The second module is configured to, based on the instruction signals, transfer the blocks of data between the first module and the non-volatile semiconductor memory.

Abstract: Systems and methods for managing storage device commands are provided. A first storage device command is received. A first priority associated with the first storage device command is identified. A plurality of storage device commands that was received before the first storage device command is identified. Each of the plurality of storage device commands is stored in a buffer and organized in a sequence. A determination is made as to whether the first priority associated with the first storage device command is greater than a second priority associated with a second storage device command of the plurality of storage device commands. The first storage device command is added to the buffer at a first position in the sequence that is earlier than a second position of the second storage device command in response to determining the first priority is greater than the second priority.

Abstract: The present disclosure includes systems and techniques relating to adjusting bit reliability information input for decoding data stored in a memory device. In some implementations, an apparatus, systems, or methods can include a memory controller that includes circuitry configured to receive data from a memory device, where the data includes at least first and second states; circuitry configured to compare a number of the first and second states of the received data; and circuitry configured to adjust a bit reliability information input to a decoder based, at least in part, on the comparison.

Abstract: A storage drive including first, second, third, fourth and fifth modules. The first module is configured to control transfer of blocks of data between a host device and the storage drive. The second module is configured to transfer the blocks of data to and from a non-volatile semiconductor memory in the storage drive. The third module is configured to generate a first descriptor, which describes a transfer of blocks of data between the second module and the non-volatile semiconductor memory. The fourth module is configured to, according to the first descriptor, generate second descriptors. Each of the second descriptors corresponds to a respective one of the blocks of data. The fifth module is configured to generate instruction signals based on the second descriptors. The second module is configured to, based on the instruction signals, transfer the blocks of data between the first module and the non-volatile semiconductor memory.

Abstract: A thermal module for mounting to and using with a solar inverter includes a heat sink, at least one cooling module, and a thermal insulator. The heat sink has a heat-receiving portion and a heat-radiating portion, and the cooling module has a hot side and a cold side. The hot side of the cooling module is in contact with the heat-receiving portion of the heat sink while the cold side is in contact with a heat-producing source on the solar inverter. The thermal insulator is provided in a space between the heat-receiving portion of the heat sink, the cooling module, and the heat-producing source of the solar inverter. With the cooling module provided between the heat sink and the solar inverter, the solar inverter can have largely upgraded heat dissipation efficiency.

Abstract: A thermal module for mounting to and using with a solar inverter includes a heat sink, at least one cooling module, and a thermal insulator. The heat sink has a heat-receiving portion and a heat-radiating portion, and the cooling module has a hot side and a cold side. The hot side of the cooling module is in contact with the heat-receiving portion of the heat sink while the cold side is in contact with a heat-producing source on the solar inverter. The thermal insulator is provided in a space between the heat-receiving portion of the heat sink, the cooling module, and the heat-producing source of the solar inverter. With the cooling module provided between the heat sink and the solar inverter, the solar inverter can have largely upgraded heat dissipation efficiency.