Patents by Inventor Jin-Man Han

Jin-Man Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11938781
    Abstract: A vehicular heat management system includes a refrigerant circulation line configured to generate hot energy or cold energy depending on a flow direction of a refrigerant, a heater core side coolant circulation line configured to transfer refrigerant heat generated in the refrigerant circulation line to a heater core to heat a passenger compartment, and a battery side coolant circulation line configured to receive coolant heat of the heater core side coolant circulation line via a coolant and then circulate the coolant through a battery to preheat the battery.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: March 26, 2024
    Assignee: Hanon Systems
    Inventors: Hyeon Gyu Kim, Doo Hoon Kim, Kyung Ju An, Byeong Ha Lee, Jin Jae Lee, Joong Man Han
  • Patent number: 11936029
    Abstract: A vehicular heat management system for individually cooling and heating a plurality of air conditioning regions of a vehicle includes a plurality of refrigerant circulation lines configured to cool and heat the air conditioning regions individually shared by the refrigerant circulation lines. The refrigerant circulation lines are provided with one or more air conditioning units for individually cooling and heating the respective air conditioning regions, and are configured to supply a refrigerant to the corresponding air conditioning units to individually cool and heat the air conditioning regions corresponding to the air conditioning units.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: March 19, 2024
    Assignee: Hanon Systems
    Inventors: Doo Hoon Kim, Hyeon Gyu Kim, Kyung Ju An, Jin Jae Lee, Joong Man Han
  • Patent number: 10718672
    Abstract: A piezoelectric device package includes a board having a lower surface and an upper surface, a plurality of terminals disposed on the lower surface, a piezoelectric device disposed on the upper surface, a thermistor layer and a resistance layer disposed on the lower surface, and a cap lead covering an upper portion of the board.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: July 21, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jin Man Han, Yong Sung Kim, Sang Yeob Cha, Young Key Kim
  • Patent number: 10573378
    Abstract: Methods of operating non-volatile memory devices are provided including receiving program data and a program address. Memory cells that correspond to the program address are selected from among memory cells in an erased state. The selected memory cells are programmed based on the program data such that each of the selected memory cells is programmed to one of a plurality of programmed states, where threshold voltage distributions of the programmed states are different from each other and are higher than a threshold voltage distribution associated with the erased state. By programming all or a portion of the memory cells corresponding to the erased state to have positive threshold voltages, degradation of the data retention capability of the memory cells may be reduced.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: February 25, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Seop Shim, Jae-Hong Kim, Jin-Man Han
  • Patent number: 10104776
    Abstract: A chip resistor element includes an insulating substrate, a resistor layer, first and second internal electrodes, a resistor protection layer, first and second electrode protection layers, and first and second external electrodes. The resistor layer is on the insulating substrate, the first and second internal electrodes are on respective sides of the resistor layer, and the resistor protection layer covers the resistor layer and extends onto portions of the internal electrodes. The first electrode protection layers are on the first and second internal electrodes so as to overlap with portions of the resistor protection layer and contain first conductive powder particles and resin, while the second electrode protection layers are disposed on the first electrode protection layers and contain second conductive powder particles and resin. A content of resin in the second electrode protection layer is lower than in the first electrode protection layer.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: October 16, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jang Seok Yun, Hyung Min Kim, Jin Man Han
  • Patent number: 10061647
    Abstract: In a method of operating a nonvolatile memory device, a plurality of pages of a first memory block of a plurality of memory blocks of a memory cell array are programmed. After programming, a dummy pulse is applied to at least some of the plurality of memory blocks at least once before a read operation on is performed on one of the plurality of pages.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: August 28, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Seop Shim, Jae-Hong Kim, Sang-Soo Cha, Jin-Man Han
  • Publication number: 20180209855
    Abstract: A piezoelectric device package includes a board having a lower surface and an upper surface, a plurality of terminals disposed on the lower surface, a piezoelectric device disposed on the upper surface, a thermistor layer and a resistance layer disposed on the lower surface, and a cap lead covering an upper portion of the board.
    Type: Application
    Filed: September 22, 2017
    Publication date: July 26, 2018
    Inventors: Jin Man HAN, Yong Sung KIM, Sang Yeob CHA, Young Key KIM
  • Publication number: 20180040368
    Abstract: Methods of operating non-volatile memory devices are provided including receiving program data and a program address. Memory cells that correspond to the program address are selected from among memory cells in an erased state. The selected memory cells are programmed based on the program data such that each of the selected memory cells is programmed to one of a plurality of programmed states, where threshold voltage distributions of the programmed states are different from each other and are higher than a threshold voltage distribution associated with the erased state. By programming all or a portion of the memory cells corresponding to the erased state to have positive threshold voltages, degradation of the data retention capability of the memory cells may be reduced.
    Type: Application
    Filed: October 13, 2017
    Publication date: February 8, 2018
    Inventors: Young-Seop SHIM, Jae-Hong KIM, Jin-Man HAN
  • Patent number: 9818477
    Abstract: A method of operating a non-volatile memory device includes receiving program data and a program address. Memory cells that correspond to the program address are selected from among memory cells in an erased state. The selected memory cells are programmed based on the program data such that each of the selected memory cells is programmed to one of a plurality of programmed states, where threshold voltage distributions of the programmed states are different from each other and are higher than a threshold voltage distribution associated with the erased state. By programming all or a portion of the memory cells corresponding to the erased state to have positive threshold voltages, degradation of the data retention capability of the memory cells may be reduced.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: November 14, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Seop Shim, Jae-Hong Kim, Jin-Man Han
  • Publication number: 20170202089
    Abstract: A chip resistor element includes an insulating substrate, a resistor layer, first and second internal electrodes, a resistor protection layer, first and second electrode protection layers, and first and second external electrodes. The resistor layer is on the insulating substrate, the first and second internal electrodes are on respective sides of the resistor layer, and the resistor protection layer covers the resistor layer and extends onto portions of the internal electrodes. The first electrode protection layers are on the first and second internal electrodes so as to overlap with portions of the resistor protection layer and contain first conductive powder particles and resin, while the second electrode protection layers are disposed on the first electrode protection layers and contain second conductive powder particles and resin. A content of resin in the second electrode protection layer is lower than in the first electrode protection layer.
    Type: Application
    Filed: November 2, 2016
    Publication date: July 13, 2017
    Inventors: Jang Seok YUN, Hyung Min KIM, Jin Man HAN
  • Patent number: 9691838
    Abstract: A chip resistor includes a substrate having first and second electrodes disposed on one surface thereof to be separated from each other. A first resistor electrically connects the first electrode to the second electrode, and a second resistor electrically connects the first electrode to the second electrode. When temperatures of the first electrode and the second electrode are different from each other, thermo electromotive force generated from the first resistor is less than thermo electromotive force generated from the second resistor, and a temperature coefficient of resistivity (TCR) of the second resistor is lower than the TCR of the first resistor.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: June 27, 2017
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jin Man Han, Jang Seok Yun
  • Publication number: 20170179217
    Abstract: A chip resistor includes a substrate having first and second electrodes disposed on one surface thereof to be separated from each other. A first resistor electrically connects the first electrode to the second electrode, and a second resistor electrically connects the first electrode to the second electrode. When temperatures of the first electrode and the second electrode are different from each other, thermo electromotive force generated from the first resistor is less than thermo electromotive force generated from the second resistor, and a temperature coefficient of resistivity (TCR) of the second resistor is lower than the TCR of the first resistor.
    Type: Application
    Filed: August 5, 2016
    Publication date: June 22, 2017
    Inventors: Jin Man HAN, Jang Seok YUN
  • Publication number: 20170062065
    Abstract: In a method of operating a nonvolatile memory device, a plurality of pages of a first memory block of a plurality of memory blocks of a memory cell array are programmed. After programming, a dummy pulse is applied to at least some of the plurality of memory blocks at least once before a read operation on is performed on one of the plurality of pages.
    Type: Application
    Filed: August 15, 2016
    Publication date: March 2, 2017
    Inventors: Young-Seop Shim, Jae-Hong KIM, Sang-Soo CHA, Jin-Man HAN
  • Publication number: 20160372185
    Abstract: A method of operating a non-volatile memory device includes receiving program data and a program address. Memory cells that correspond to the program address are selected from among memory cells in an erased state. The selected memory cells are programmed based on the program data such that each of the selected memory cells is programmed to one of a plurality of programmed states, where threshold voltage distributions of the programmed states are different from each other and are higher than a threshold voltage distribution associated with the erased state. By programming all or a portion of the memory cells corresponding to the erased state to have positive threshold voltages, degradation of the data retention capability of the memory cells may be reduced.
    Type: Application
    Filed: February 26, 2016
    Publication date: December 22, 2016
    Inventors: Young-Seop Shim, Jae-Hong Kim, Jin-Man Han
  • Patent number: 9230658
    Abstract: Methods and apparatus are disclosed, such as those involving a flash memory device. One such method includes storing data on memory cells on a memory block including a plurality of word lines and a plurality of memory cells on the word lines. The word lines comprising one or more bottom edge word lines, one or more top edge word lines, and intermediate word lines between the bottom and top edge word lines. The data is stored first on memory cells on the intermediate word lines. Then, a remaining portion, if any, of the data is stored on memory cells on the bottom edge word lines and/or the top edge word lines. This method enhances the life of the flash memory by preventing a premature failure of memory cells on the bottom or top edge word lines, which can be more prone to failure.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: January 5, 2016
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Jin-Man Han
  • Patent number: 9147492
    Abstract: According to example embodiments, a control method of a nonvolatile memory device, which includes a plurality of memory blocks on a substrate, each memory block including a plurality of sub blocks stacked in a direction perpendicular to the substrate and being configured to be erased independently and each sub block including a plurality of memory cells stacked in the direction perpendicular to the substrate. The control method includes comparing a count value of a first memory block with a reference value, the count value determined according to the number of program, read, or erase operations executed at the first memory block after data is programmed in the first memory block; and if the count value is greater than or equal to the reference value, performing a reprogram operation in which data programmed in first the memory block is read and the read data is programmed in a second memory block.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: September 29, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sunil Shim, Jin-Man Han, Sang-Wan Nam, Won-Taeck Jung
  • Patent number: 9070459
    Abstract: Apparatus, systems, and methods may operate to receive an external erase command at a control circuit coupled to an erasable memory array located on a substrate. A global select gate voltage may thereafter be enabled for application to wordline transistors coupled to the erasable memory array after a voltage applied to the substrate has reached a preselected initiation voltage level between about zero volts and an ultimate erase voltage.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: June 30, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Xiaojun Yu, Jin-man Han, Aaron Yip
  • Publication number: 20150078087
    Abstract: According to example embodiments, a control method of a nonvolatile memory device, which includes a plurality of memory blocks on a substrate, each memory block including a plurality of sub blocks stacked in a direction perpendicular to the substrate and being configured to be erased independently and each sub block including a plurality of memory cells stacked in the direction perpendicular to the substrate. The control method includes comparing a count value of a first memory block with a reference value, the count value determined according to the number of program, read, or erase operations executed at the first memory block after data is programmed in the first memory block; and if the count value is greater than or equal to the reference value, performing a reprogram operation in which data programmed in first the memory block is read and the read data is programmed in a second memory block.
    Type: Application
    Filed: November 18, 2014
    Publication date: March 19, 2015
    Inventors: Sunil SHIM, Jin-Man HAN, Sang-Wan NAM, Won-Taeck JUNG
  • Patent number: 8772857
    Abstract: A vertical memory device includes a channel, a ground selection line (GSL), word lines and a string selection line (SSL). The channel extends in a first direction substantially perpendicular to a top surface of a substrate, and a thickness of the channel is different according to height. The GSL, the word lines and the SSL are sequentially formed on a sidewall of the channel in the first direction and spaced apart from each other.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: July 8, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byeong-In Choe, Jae-Hoon Jang, Sun-Il Shim, Han-Soo Kim, Jin-Man Han
  • Patent number: 8698593
    Abstract: There is provided a chip resistor including a ceramic substrate; a first resistance layer formed on the ceramic substrate and including a first conductive metal and a first glass; and a second resistance layer formed on the first resistance layer, including a second conductive metal and a second glass, and having a smaller content of glass than the first resistance layer, thereby obtaining relatively low resistance and a relatively small temperature coefficient of resistance (TCR).
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: April 15, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jang Ho Park, Young Key Kim, Ki Won Suh, Jang Seok Yun, Jin Man Han, Sung Jun Kim