Abstract: The present invention discloses a double access path mask read-only memory cell array structure, characterized in that the stored data is accessed simultaneously through two access paths disposed on both sides of a memory cell array structure. The reliability is improved since the value 0 or 1 stored in the data can be accessed through two paths and the operation speed is enhanced since the resistance in the conductive path from the sense amplifier to the ground is effectively reduced when accessing 0.

Abstract: The present invention discloses a double access path mask read-only memory cell array structure, characterized in that the stored data is accessed simultaneously through two access paths disposed on both sides of a memoery cell array structure. The reliability is improved since the value 0 or 1 stored in the data can be accessed through two paths and the operation speed is enhanced since the resistance in the conductive path from the sense amplifier to the ground is effectively reduced when accessing 0.

Abstract: A circuit and algorithm for multiplying three matrices includes plurality of processor element (PE) column. Each PE column includes a plurality of processor element (PE) units and each unit includes a data register for receiving and storing a plurality sets of numbers of a row of a first matrix and a corresponding column of a second matrix. Each of the PE units is connected to another PE units of the PE column sequentially transmitting the sets of numbers between the registers in a time progressive manner. Each of the PE units further includes a multiplication processing unit for receiving a plurality of bits of the sets of numbers from the ?storage means! register, the multiplication processing unit processes the plurality of bits to generate a partial processing result At least one of the PE units using the partial processing result generates a multiplication of the sets of numbers whereby each of the PE column performs a matrix multiplication of a column of the second matrix.

Abstract: A DCT circuit has a pre-processor stage which receives each element x.sub.ij i,j=1,2, . . . ,N, where N is an integer.gtoreq.4, of an input matrix X. The pre-processor stage simultaneously outputs Q.gtoreq.1 sequences of one or more columns of elements of a matrix A.sub.f having elements a.sub.ij =x.sub.ij +x.sub.(N-i+1)j i=1,2, . . . ,N/2, j=1,2, . . . ,N and Q.gtoreq.1 sequences of one or more columns of elements of a matrix A.sub.r having elements a.sub.ij =x.sub.(i-N/2)j -x.sub.(3N/2-i+1)j i=N/2+1, N/2+2, . . . ,N j=1,2, . . . ,N. The DCT circuit also has a 1-D DCT processing stage which simultaneously receives each of the 2Q sequences of elements outputted by the pre-processor stage, P sequences of one or more rows of elements of an N/2.times.N/2 DCT cosine coefficient matrix C.sub.1 and P sequences of rows of elements of an N/2.times.N/2 DCT cosine coefficient matrix C.sub.2. The 1-D DCT processing stage has K.gtoreq.

Abstract: A transpose memory is disclosed which has four dual port memories, a first counter for writing elements in the dual port memories and a second counter for reading out elements from the dual port memories. If the received matrix is to be outputted to the first type of transform circuit, the first counter writes each matrix element in a particular dual port memory assigned to the quadrant of the matrix element. If the received matrix is to be outputted to the second type of transform circuit, the first counter writes each matrix element in a particular dual port memory assigned to the "evenness" or "oddness" (i.e., divisibleness by two) of the row and column of the matrix element.

Abstract: A circuit and algorithm for multiplying three matrices is disclosed having a first multiplication stage for multiplying a first matrix with a second matrix to produce an intermediate product matrix. Additionally, the circuit and algorithm have a second stage for multiplying a third matrix with the intermediate product matrix to compute the final product matrix. Each stage is provided with a plurality of bit processing element pipelines for generating the elements of the product matrix of that stage. In each stage, one pipeline is provided for generating each column of the product matrix and each pipeline within a stage operates in parallel with the other pipelines of that stage.