Abstract: A memory device and an operation method thereof is disclosed. The memory device includes a SRAM cell and a power supply assist circuit connected to the SRAM cell. The power supply assist circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. The first transistor receives a power supply voltage. The control terminals of the first transistor and the second transistor are connected to each other. The third transistor switches, in response to a first control signal, to connect the control terminal and the connect terminal of the second transistor. The fourth transistor switches, in response to a second control signal, to drive the control terminal of the second transistor to a system ground voltage. The fifth transistor switches, in response to a third control signal, to drive the control terminal of the first transistor to the power supply voltage.

Abstract: A personalized voice conversion system includes a cloud server and an intelligent device that communicates with the cloud server. The intelligent device upstreams an original voice signal to the cloud server. The cloud server converts the original voice signal into an intelligible voice signal based on an intelligible voice conversion model. The intelligent device downloads and plays the intelligible voice signal. Based on the original voice signal and the corresponding intelligible voice signal, the cloud server and the intelligent device train an off-line voice conversion model provided to the intelligent device. When the intelligent device stops communicating with the cloud server, the intelligent device converts a new original voice signal into a new intelligible voice signal based on the off-line voice conversion model and plays the new intelligible voice signal.

Abstract: A memory device and an operation method thereof is disclosed. The memory device includes a SRAM cell and a power supply assist circuit connected to the SRAM cell. The power supply assist circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. The first transistor receives a power supply voltage. The control terminals of the first transistor and the second transistor are connected to each other. The third transistor switches, in response to a first control signal, to connect the control terminal and the connect terminal of the second transistor. The fourth transistor switches, in response to a second control signal, to drive the control terminal of the second transistor to a system ground voltage. The fifth transistor switches, in response to a third control signal, to drive the control terminal of the first transistor to the power supply voltage.

Abstract: A personalized voice conversion system includes a cloud server and an intelligent device that communicates with the cloud server. The intelligent device upstreams an original voice signal to the cloud server. The cloud server converts the original voice signal into an intelligible voice signal based on an intelligible voice conversion model. The intelligent device downloads and plays the intelligible voice signal. Based on the original voice signal and the corresponding intelligible voice signal, the cloud server and the intelligent device train an off-line voice conversion model provided to the intelligent device. When the intelligent device stops communicating with the cloud server, the intelligent device converts a new original voice signal into a new intelligible voice signal based on the off-line voice conversion model and plays the new intelligible voice signal.

Abstract: A memory device and an operation method thereof is disclosed. The memory device includes a static random access memory (SRAM) cell, a power-supply assist-voltage generator circuit, a source assist-voltage generator circuit, and a word-line assist-voltage generator circuit. The power-supply assist-voltage generator circuit, the source assist-voltage generator circuit, and the word-line assist-voltage generator circuit lower the effective supply voltage for un-accessed rows of memory cells in the hold mode, increase the effective supply voltage for accessed memory cells in the active mode, and lower the effective supply voltage further for all the SRAM cells in the standby mode to achieve a solution for active and standby power reduction besides achieving the stability and noise margins.

Abstract: A variable-latency computing device includes a computing module, enabling units, a storage operation unit, and a detecting controller. The enabling units are divided into at least two groups. The storage operation unit includes word lines and bit lines. The enabling units enable the word line. The storage operation unit accumulates the data values corresponding to the bit lines and the enabled word line, thereby computing first accumulation values. The detecting controller controls the computing module to stop receiving the first accumulation values when the sum of the first accumulation values is higher than a threshold value and takes turns to turn off the at least two groups. The storage operation unit computes second accumulation values during different periods. The computing module receives and computes the second accumulation values corresponding to the at least two groups, so as to generate a computation value.

Abstract: A memory device and an operation method thereof is disclosed. The memory device includes a static random access memory (SRAM) cell, a power-supply assist-voltage generator circuit, a source assist-voltage generator circuit, and a word-line assist-voltage generator circuit. The power-supply assist-voltage generator circuit, the source assist-voltage generator circuit, and the word-line assist-voltage generator circuit lower the effective supply voltage for un-accessed rows of memory cells in the hold mode, increase the effective supply voltage for accessed memory cells in the active mode, and lower the effective supply voltage further for all the SRAM cells in the standby mode to achieve a solution for active and standby power reduction besides achieving the stability and noise margins.

Abstract: A single-ended sense amplifier includes a virtual-supply voltage-adapted (VVDD-adapted) inverter circuit, a virtual-supply voltage-adapted (VVDD-adapted) voltage-level converter circuit (VLC), and a virtual-supply-voltage-adaptation circuit (VSVA). The single-ended sense amplifier receives a data signal input, a sensing-operation-enabling signal input, and a pre-charging control signal input to generate a final amplified signal output. There are a first virtual-supply node and a second virtual-supply node in the VVDD-adapted inverter circuit. There is a third virtual-supply node in the VVDD-adapted VLC. The VSVA connects both the first and third virtual supply voltage nodes. The output end of the virtual-supply voltage-adapted inverter circuit connects to the input end of the VVDD-adapted VLC.

Abstract: A time detection circuit and a time detection method are provided. The time detection circuit includes an input signal processor and a time signal amplifier. The input signal processor receives a first input signal and a second input signal, calculates a time difference value between the first input signal and the second input signal, adjusts the time difference value by comparing the time difference value with a set reference value, and provides the adjusted time difference value. The time signal amplifier receives the adjusted time difference value, and amplifies the adjusted time difference value to generate an amplified time signal. The time signal amplifier operates in a linear operation region between a first time value and a second time value, and the set reference value is set according to the first time value and the second time value.

Abstract: A computation speed compensation circuit and a compensation method thereof are provided. The computation speed compensation circuit includes a power selection circuit and a computation speed sensor. The power selection circuit selects one of a first power and a second power as a supplied power according to a first control signal. The computation speed sensor detects a response speed of a first detection signal at a first intermediate transmission point of a computation circuit to generate the first control signal. A voltage value of the first power is lower than a voltage value of the second power, and the supplied power is received by a computation circuit as an operation power of the computation circuit.

Abstract: A computation speed compensation circuit and a compensation method thereof are provided. The computation speed compensation circuit includes a power selection circuit and a computation speed sensor. The power selection circuit selects one of a first power and a second power as a supplied power according to a first control signal. The computation speed sensor detects a response speed of a first detection signal at a first intermediate transmission point of a computation circuit to generate the first control signal. A voltage value of the first power is lower than a voltage value of the second power, and the supplied power is received by a computation circuit as an operation power of the computation circuit.

Abstract: The present invention discloses a speculative lookahead processing device and method to enhance the statistical performance of datapaths. The method comprises steps: entering an input signal to at least two datapath units in a round-robin way; outputting the correct value at the Nth cycle, and acquiring the speculation value at the Mth cycle beforehand to start the succeeding computation, wherein M and N are natural numbers and M is smaller than N; comparing the speculation value with the correct value at the Nth cycle to determine whether the speculation is successful; if successful, excluding extra activities; if not successful, deleting the succeeding computation undertaken beforehand and restarting the succeeding computation with the correct value.

Abstract: A static random access memory cell includes a controlling signal line unit, a latch and an access transistor unit. The first bottom transistor unit is controlled by the controlling signal line unit to change voltage levels of the first pseudo node and the second pseudo node. The second bottom transistor unit is controlled by the first internal node to perform connection and disconnection between the controlling signal line unit and the second pseudo node, and the second bottom transistor unit is controlled by the second internal node to perform connection and disconnection between the controlling signal line unit and the first pseudo node. The access transistor unit is controlled by the controlling signal line unit to perform connection and disconnection between the controlling signal line unit, the first pseudo node and the second pseudo node.

Abstract: A static random access memory cell includes a controlling signal line unit, a latch and an access transistor unit. The first bottom transistor unit is controlled by the controlling signal line unit to change voltage levels of the first pseudo node and the second pseudo node. The second bottom transistor unit is controlled by the first internal node to perform connection and disconnection between the controlling signal line unit and the second pseudo node, and the second bottom transistor unit is controlled by the second internal node to perform connection and disconnection between the controlling signal line unit and the first pseudo node. The access transistor unit is controlled by the controlling signal line unit to perform connection and disconnection between the controlling signal line unit, the first pseudo node and the second pseudo node.

Abstract: An apparatus for jitter measurement includes a first delay circuit, a second delay circuit, and a control circuit. The first delay circuit imposes a preliminary phase delay on an input signal to generate a delayed input signal. The second delay circuit operates with the first delay circuit to impose a fine phase delay on the delayed input signal. The control circuit controls amounts of delays imposed by the first and second delay circuits, and fine tunes the phase delay of the delayed input signal according to the amounts of delays respectively imposed by delay elements of the first and second delay circuits, and estimates or calculates a jitter window for the input signal according to adjustment results of the first and second delay circuits.

Abstract: A device for detecting and correcting timing error and a method for designing typical-case timing using the same is disclosed. The device includes two datapath units connected with first and second multiplexers and two transition detectors. Each datapath unit receives and calculates an input signal to generate a speculation value and a correct value. Then, the speculation value and the correct value are transmitted to the first and second multiplexers and the transition detectors determine whether transition of the outputted speculation value is unstable. If yes, the datapath unit outputting the speculation value is stalled for a period of time for correction, whereby the second multiplexer outputs the correct value. If no, the datapath unit outputs the speculation value, then the present invention uses the undertaken timing as a setting specification to complete a circuit design. The present invention can improve system efficiency and power of the whole circuit.

Abstract: An apparatus for jitter measurement includes a first delay circuit, a second delay circuit, and a control circuit. The first delay circuit imposes a preliminary phase delay on an input signal to generate a delayed input signal. The second delay circuit operates with the first delay circuit to impose a fine phase delay on the delayed input signal. The control circuit controls amounts of delays imposed by the first and second delay circuits, and fine tunes the phase delay of the delayed input signal according to the amounts of delays respectively imposed by delay elements of the first and second delay circuits, and estimates or calculates a jitter window for the input signal according to adjustment results of the first and second delay circuits.

Abstract: The present invention discloses a speculative lookahead processing device and method to enhance the statistical performance of datapaths. The method comprises steps: entering an input signal to at least two datapath units in a round-robin way; outputting the correct value at the Nth cycle, and acquiring the speculation value at the Mth cycle beforehand to start the succeeding computation, wherein M and N are natural numbers and M is smaller than N; comparing the speculation value with the correct value at the Nth cycle to determine whether the speculation is successful; if successful, excluding extra activities; if not successful, deleting the succeeding computation undertaken beforehand and restarting the succeeding computation with the correct value.

Abstract: A dynamic voltage scaling system having time borrowing and local boosting capability, including: a time borrowing circuit and a local boost circuit. The time borrowing circuit connected electrically between a primary stage logic circuit and a secondary stage logic circuit is activated by an all-domain clock signal, and then generates an output data to the secondary stage logic circuit based on input data to the primary stage logic circuit. The local boost circuit is connected to a low working voltage line, when input data of the time borrowing circuit lags behind a positive level of said all-domain clock signal, the time borrowing circuit delays fetching data by a flip flop and changes state to produce a warning signal, so that the local boost circuit disconnects its connection with said low working voltage line, and is connected electrically to a high working voltage line.

Abstract: A NOR-type ROM with hierarchical-BL structure, dynamic segmentation shielding, and source programming includes a plurality of bitcells forming a plurality of cell arrays, a plurality of WLs, a plurality of local bit lines LBLs electrically connected with the drains of the bitcells, a plurality of odd/even selection circuits electrically connected the LBLs that the bitcells in one of the cell array correspond to, a plurality of GBLs electrically connected the odd/even selection circuits that the bitcells in columns correspond to, and a plurality of odd-even precharge circuits electrically connected with the GBLs. The source of each bitcell is selectively grounded or floating according to the code-pattern.