Patents by Inventor Jinnie Aloysius

Jinnie Aloysius has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220173034
    Abstract: An integrated circuit interconnect structure includes a first metallization level including a first metal line having a first sidewall and a second sidewall extending a length in a first direction. A second metal line is adjacent to the first metal line and a dielectric is between the first metal line and the second metal line. A second metallization level is above the first metallization level where the second metallization level includes a third metal line extending a length in a second direction orthogonal to the first direction. The third metal line extends over the first metal line and the second metal line but not beyond the first sidewall. A conductive via is between the first metal line and the third metal line where the conductive via does not extend beyond the first sidewall or beyond the second sidewall.
    Type: Application
    Filed: February 14, 2022
    Publication date: June 2, 2022
    Applicant: Intel Corporation
    Inventors: Manish Chandhok, Leonard Guler, Paul Nyhus, Gobind Bisht, Jonathan Laib, David Shykind, Gurpreet Singh, Eungnak Han, Noriyuki Sato, Charles Wallace, Jinnie Aloysius
  • Publication number: 20220102210
    Abstract: Contact over active gate (COAG) structures are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. A remnant of a di-block-co-polymer is over a portion of the plurality of gate structures or the plurality of conductive trench contact structures. An interlayer dielectric material is over the di-block-co-polymer, over the plurality of gate structures, and over the plurality of conductive trench contact structures. An opening in the interlayer dielectric material. A conductive structure is in the opening, the conductive structure in direct contact with a corresponding one of the trench contact structures or with a corresponding one of the gate contact structures.
    Type: Application
    Filed: September 25, 2020
    Publication date: March 31, 2022
    Inventors: Paul A. NYHUS, Charles H. WALLACE, Manish CHANDHOK, Mohit K. HARAN, Gurpreet SINGH, Eungnak HAN, Florian GSTREIN, Richard E. SCHENKER, David SHYKIND, Jinnie ALOYSIUS, Sean PURSEL
  • Patent number: 11251117
    Abstract: An integrated circuit interconnect structure includes a first metallization level including a first metal line having a first sidewall and a second sidewall extending a length in a first direction. A second metal line is adjacent to the first metal line and a dielectric is between the first metal line and the second metal line. A second metallization level is above the first metallization level where the second metallization level includes a third metal line extending a length in a second direction orthogonal to the first direction. The third metal line extends over the first metal line and the second metal line but not beyond the first sidewall. A conductive via is between the first metal line and the third metal line where the conductive via does not extend beyond the first sidewall or beyond the second sidewall.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: February 15, 2022
    Assignee: Intel Corporation
    Inventors: Manish Chandhok, Leonard Guler, Paul Nyhus, Gobind Bisht, Jonathan Laib, David Shykind, Gurpreet Singh, Eungnak Han, Noriyuki Sato, Charles Wallace, Jinnie Aloysius
  • Publication number: 20210074632
    Abstract: An integrated circuit interconnect structure includes a first metallization level including a first metal line having a first sidewall and a second sidewall extending a length in a first direction. A second metal line is adjacent to the first metal line and a dielectric is between the first metal line and the second metal line. A second metallization level is above the first metallization level where the second metallization level includes a third metal line extending a length in a second direction orthogonal to the first direction. The third metal line extends over the first metal line and the second metal line but not beyond the first sidewall. A conductive via is between the first metal line and the third metal line where the conductive via does not extend beyond the first sidewall or beyond the second sidewall.
    Type: Application
    Filed: September 5, 2019
    Publication date: March 11, 2021
    Applicant: Intel Corporation
    Inventors: Manish Chandhok, Leonard Guler, Paul Nyhus, Gobind Bisht, Jonathan Laib, David Shykind, Gurpreet Singh, Eungnak Han, Noriyuki Sato, Charles Wallace, Jinnie Aloysius