Patents by Inventor Jinning Liu

Jinning Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220374578
    Abstract: Ground rule verification (“GRV”) design layouts may be automatically generated based on one or more design macros. The GRV design layout may be tested based on the one or more design macros by violating one or more ground rules using one or more GRV ranges. The testing may include electrical testing of the one or more GRV design layouts based on the one or more design macros. The one or more ground rules may be automatically selected and approved the based upon a degree of violation acceptability.
    Type: Application
    Filed: May 21, 2021
    Publication date: November 24, 2022
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: JINGYU LIAN, SHRUTHI VENKATESHAN, TENKO YAMASHITA, JINNING LIU
  • Publication number: 20220328873
    Abstract: A polyoxymethylene-based all-solid-state polymer electrolyte prepared by in-situ ring-opening polymerization is used in forming an all-solid-state secondary lithium battery. A trioxymethylene monomer, an additive and lithium salt initiates in-situ ring-opening polymerization on a porous support material through a catalyst to form the all-solid-state polymer electrolyte, which has a thickness of 10 ?m-800 ?m, an ionic conductivity of 4×10?5 S/cm—8×10?3 S/cm at room temperature and an electrochemical window not lower than 4.2 V.
    Type: Application
    Filed: June 24, 2022
    Publication date: October 13, 2022
    Inventors: Guanglei CUI, Jianjun ZHANG, Han WU, Tingting LIU, Jinning ZHANG, Ben TANG, Zhe YU, Hongxia XU
  • Patent number: 10621295
    Abstract: A system and method to perform risk assessment or design rule determination for an integrated circuit involves generating two or more process variation contours based on corresponding two or more combinations of two or more factors that affect manufacturability of the integrated circuit. Each of the two or more process variation contours is associated with a probability. The method also includes generating a random number to select from among the two or more process variation contours based on a cumulative probability value associated with each of the two or more process variation contours. The cumulative probability values are determined from the probabilities. The risk assessment or the design rule determination is performed using selected ones of the two or more process variation contours. Fabrication yield is increased based on finalizing the physical layout using the process variation contours.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: April 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jinning Liu, Jing Sha, Robert Wong, Dongbing Shao
  • Publication number: 20190311071
    Abstract: A system and method to perform risk assessment or design rule determination for an integrated circuit involves generating two or more process variation contours based on corresponding two or more combinations of two or more factors that affect manufacturability of the integrated circuit. Each of the two or more process variation contours is associated with a probability. The method also includes generating a random number to select from among the two or more process variation contours based on a cumulative probability value associated with each of the two or more process variation contours. The cumulative probability values are determined from the probabilities. The risk assessment or the design rule determination is performed using selected ones of the two or more process variation contours. Fabrication yield is increased based on finalizing the physical layout using the process variation contours.
    Type: Application
    Filed: April 10, 2018
    Publication date: October 10, 2019
    Inventors: Jinning Liu, Jing Sha, Robert Wong, Dongbing Shao
  • Patent number: 7993698
    Abstract: Techniques for temperature-controlled ion implantation are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for temperature-controlled ion implantation. The apparatus may comprise at least one thermal sensor adapted to measure a temperature of a wafer during an ion implantation process inside an end station of an ion implanter. The apparatus may also comprise a thermal conditioning unit coupled to the end station. The apparatus may further comprise a controller in communication with the thermal sensor and the thermal conditioning unit, wherein the controller compares the measured temperature to a desired wafer temperature and causes the thermal conditioning unit to adjust the temperature of the wafer based upon the comparison.
    Type: Grant
    Filed: September 23, 2006
    Date of Patent: August 9, 2011
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Julian Blake, Jonathan England, Scott Holden, Steven R. Walther, Reuel Liebert, Richard S. Muka, Ukyo Jeong, Jinning Liu, Kyu-Ha Shim, Sandeep Mehta
  • Publication number: 20080076194
    Abstract: Techniques for temperature-controlled ion implantation are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for temperature-controlled ion implantation. The apparatus may comprise at least one thermal sensor adapted to measure a temperature of a wafer during an ion implantation process inside an end station of an ion implanter. The apparatus may also comprise a thermal conditioning unit coupled to the end station. The apparatus may further comprise a controller in communication with the thermal sensor and the thermal conditioning unit, wherein the controller compares the measured temperature to a desired wafer temperature and causes the thermal conditioning unit to adjust the temperature of the wafer based upon the comparison.
    Type: Application
    Filed: September 23, 2006
    Publication date: March 27, 2008
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Julian Blake, Jonathan England, Scott Holden, Steven R. Walther, Reuel Liebert, Richard S. Muka, Ukyo Jeong, Jinning Liu, Kyu-Ha Shim, Sandeep Mehta
  • Patent number: 6756600
    Abstract: A method of increasing ion source lifetime in an ion implantation system uses the introduction of an inert gas, such as argon or xenon, into the halide-containing source gas. Inert gas constituents have a cleansing effect in the plasma ambient by enhancing sputtering.
    Type: Grant
    Filed: February 19, 1999
    Date of Patent: June 29, 2004
    Assignees: Advanced Micro Devices, Inc., Varian Associates, Inc.
    Inventors: Che-Hoo Ng, Emi Ishida, Jaime M. Reyes, Jinning Liu, Sandeep Mehta
  • Publication number: 20020000523
    Abstract: A method of increasing ion source lifetime in an ion implantation system uses the introduction of an inert gas, such as argon or xenon, into the halide-containing source gas. Inert gas constituents have a cleansing effect in the plasma ambient by enhancing sputtering.
    Type: Application
    Filed: February 19, 1999
    Publication date: January 3, 2002
    Inventors: CHE-HOO NG, EMI ISHIDA, JAIME M. REYES, JINNING LIU, SANDEEP MEHTA