Abstract: An electronic display panel comprising a plastic substrate; a bottom shield metal (BSM) on the plastic substrate; a thin-film transistor (TFT) on the BSM, the TFT and the BSM at least partially overlapping each other; and an active buffer layer between the TFT and the BSM, wherein the BSM is connected to one of a gate electrode, a source electrode, and a drain electrode of the TFT. A bottom shield metal (BSM) on the plastic substrate, the BSM located to minimize formation of a back channel in a pixel circuit by trapped charges of the plastic substrate, the pixel circuit in a pixel area defined by a gate line and a data line on the plastic substrate, the pixel circuit on the active buffer layer including a plurality of TFTs and a plurality of component interconnecting nodes.

Abstract: Disclosed herein is a bidirectional shift register which is capable of preventing multi-outputs from both end stages. The shift register includes a plurality of stages for outputting scan pulses forward or reversely based on a start pulse and a plurality of clock pulses with a phase difference. A last one of the stages includes a forward scan controller for making a set node active and a reset node inactive based on any one of the clock pulses and a scan pulse from an upstream stage, a reverse scan controller for making the set node active and the reset node inactive based on any one of the clock pulses and the start pulse, and an output unit for outputting any one of a corresponding scan pulse and a deactivation voltage based on a voltage at the set node, a voltage at the reset node and any one of the clock pulses.

Abstract: An electronic display panel comprising a plastic substrate; a bottom shield metal (BSM) on the plastic substrate; a thin-film transistor (TFT) on the BSM, the TFT and the BSM at least partially overlapping each other; and an active buffer layer between the TFT and the BSM, wherein the BSM is connected to one of a gate electrode, a source electrode, and a drain electrode of the TFT. A bottom shield metal (BSM) on the plastic substrate, the BSM located to minimize formation of a back channel in a pixel circuit by trapped charges of the plastic substrate, the pixel circuit in a pixel area defined by a gate line and a data line on the plastic substrate, the pixel circuit on the active buffer layer including a plurality of TFTs and a plurality of component interconnecting nodes.

Abstract: Disclosed herein is a bidirectional shift register which is capable of preventing multi-outputs from both end stages. The shift register includes a plurality of stages for outputting scan pulses forward or reversely based on a start pulse and a plurality of clock pulses with a phase difference. A last one of the stages includes a forward scan controller for making a set node active and a reset node inactive based on any one of the clock pulses and a scan pulse from an upstream stage, a reverse scan controller for making the set node active and the reset node inactive based on any one of the clock pulses and the start pulse, and an output unit for outputting any one of a corresponding scan pulse and a deactivation voltage based on a voltage at the set node, a voltage at the reset node and any one of the clock pulses.

Abstract: Disclosed herein is a bidirectional shift register which is capable of preventing multi-outputs from both end stages. The shift register includes a plurality of stages for outputting scan pulses forward or reversely based on a start pulse and a plurality of clock pulses with a phase difference. A last one of the stages includes a forward scan controller for making a set node active and a reset node inactive based on any one of the clock pulses and a scan pulse from an upstream stage, a reverse scan controller for making the set node active and the reset node inactive based on any one of the clock pulses and the start pulse, and an output unit for outputting any one of a corresponding scan pulse and a deactivation voltage based on a voltage at the set node, a voltage at the reset node and any one of the clock pulses.

Abstract: A halftone mask includes shielding parts partially formed on a transparent substrate; a lower portion halftone transmission pattern partially formed between the shielding parts on the transparent substrate; and an upper potion halftone transmission pattern partially formed on the lower portion halftone transmission layer pattern, where the lower portion halftone transmission pattern is partially exposed in a gap between the shielding parts and the upper portion halftone transmission pattern.

Abstract: A liquid crystal display device includes a first substrate, a second substrate and a liquid crystal layer between the first and second substrates. The liquid crystal display device further includes a gate line on the first substrate, a first insulation film on the gate line, a data line crossing the gate line such that the data line and the gate line define a pixel region with a transmission area and a reflection area, a thin film transistor connected to the gate line and the data line, a storage capacitor including a storage line crossing the data line and an upper storage electrode connected to the thin film transistor, a second insulation film on the thin film transistor with a transmission hole defined through the second insulation film, a reflection electrode disposed on the second insulation film in the reflection area and connected to a portion of the upper storage electrode through the transmission hole, and a pixel electrode disposed in the pixel region and connected to the reflection electrode.

Abstract: A halftone mask includes a shielding pattern partially formed on a transparent substrate; a first halftone transmission pattern partially formed on the transparent substrate; and a second halftone transmission pattern formed on the first halftone transmission layer.

Abstract: A method of fabricating a halftone mask, which includes the steps of: forming shielding patterns on a transparent substrate; forming a first halftone transmission pattern on the transparent substrate between the shielding patterns; and forming a second halftone transmission pattern on the first halftone transmission pattern, wherein a width of the second halftone transmission pattern is narrower than a width of the first halftone transmission pattern, wherein the shielding patterns are in contact with a border of the first halftone transmission pattern; and wherein portions of the first halftone transmission pattern, at gaps that are present in between the shielding patterns and the second halftone transmission pattern, are uncovered by the second halftone transmission pattern.

Abstract: A halftone mask includes a shielding pattern partially formed on a transparent substrate; a first halftone transmission pattern partially formed on the transparent substrate; and a second halftone transmission pattern formed on the first halftone transmission layer.

Abstract: A halftone mask includes a shielding pattern partially formed on a transparent substrate; a first halftone transmission pattern partially formed on the transparent substrate; and a second halftone transmission pattern formed on the first halftone transmission layer. On this halftone mask, a width of the second halftone transmission pattern is narrower than a width of the first halftone transmission pattern.

Abstract: A liquid crystal display device is provided that comprises a gate line; a first insulating film on the gate line; a data line crossing the gate line to define a pixel region, the pixel region having a transmissive area and a reflective area; a thin film transistor connected to the gate line and the data line; a pixel electrode formed in the pixel region; a second insulating film on the thin film transistor; a storage capacitor including a storage upper electrode overlapping the gate line; a transmission hole exposing at least a portion of the pixel electrode, and a reflective electrode formed in the reflective area of the pixel region, the reflective electrode connecting the pixel electrode with thin film transistor and the storage upper electrode, wherein the gate line and the pixel electrode include a first transparent conductive layer.

Abstract: A halftone mask includes a shielding pattern partially formed on a transparent substrate; a first halftone transmission pattern partially formed on the transparent substrate; and a second halftone transmission pattern formed on the first halftone transmission layer.

Abstract: A liquid crystal display device is provided that comprises a gate line; a first insulating film on the gate line; a data line crossing the gate line to define a pixel region, the pixel region having a transmissive area and a reflective area; a thin film transistor connected to the gate line and the data line; a pixel electrode formed in the pixel region; a second insulating film on the thin film transistor; a storage capacitor including a storage upper electrode overlapping the gate line; a transmission hole exposing at least a portion of the pixel electrode, and a reflective electrode formed in the reflective area of the pixel region, the reflective electrode connecting the pixel electrode with thin film transistor and the storage upper electrode, wherein the gate line and the pixel electrode include a first transparent conductive layer.

Abstract: The present application relates to a method of fabricating a display device, including the steps of forming at least one to-be-patterned material layer on a substrate and forming a photo-resist layer on the at least one to-be-patterned material layer, providing a halftone mask including light transmission parts for transmitting light, shielding parts, in which shielding patterns for intercepting the light are formed, and a halftone transmission part, in which a first halftone transmission pattern for transmitting an amount of the light that is less than an amount of an incident light and a second halftone transmission pattern formed on the first halftone transmission pattern for transmitting an amount of the light that is less than the amount of the incident light are formed, exposing the photo-resist layer to the light through the halftone mask, developing the photo-resist layer to form a photo-resist pattern on the at least one to-be-patterned material layer on the subststrate, wherein the photo-resist patt

Abstract: A liquid crystal display device is provided that comprises a gate line; a first insulating film on the gate line; a data line crossing the gate line to define a pixel region, the pixel region having a transmissive area and a reflective area; a thin film transistor connected to the gate line and the data line; a pixel electrode formed in the pixel region; a second insulating film on the thin film transistor; a storage capacitor including a storage upper electrode overlapping the gate line; a transmission hole exposing at least a portion of the pixel electrode, and a reflective electrode formed in the reflective area of the pixel region, the reflective electrode connecting the pixel electrode with thin film transistor and the storage upper electrode, wherein the gate line and the pixel electrode include a first transparent conductive layer.

Abstract: A TFT substrate having a storage capacitor with an increased capacitance and aperture ratio, and a simplified method of fabricating the same, includes gate and data lines crossing each other to define pixel areas; a gate insulating film between the gate and data lines; TFTs connected to the gate and data lines; a semiconductor pattern defining a channel of the TFTs and overlapped by the data lines; a passivation film covering the data lines and the TFTs; and at least one pixel electrode connected to a TFT and provided within a pixel hole that is arranged within a pixel area. The pixel hole is formed through the passivation film and partially through the gate insulating film. Further, a storage capacitor includes a portion of the pixel electrode that overlaps with an underlying gate line with a portion of the gate insulating film that defines the pixel hole.

Abstract: A base thin film transistor (TFT) substrate includes a substrate, array areas on the substrate; at least one dummy area on the substrate and between the array areas; an insulating film on the substrate; at least one aperture through the insulating film and arranged within the at least one dummy area; and at least one post arranged within the at least one aperture.

Abstract: A liquid crystal display device, including: a gate line on a substrate; a data line crossing the gate line with a gate insulating film therebetween to define a pixel area; a thin film transistor connected to the gate line and the data line; a semiconductor pattern which forms a channel of the thin film transistor and overlaps along the data line; a passivation film covering the data line and the thin film transistor; and a pixel electrode on the gate insulating film in a pixel hole of the pixel area that penetrates the passivation film and connected to the thin film transistor, the pixel electrode on an inclined side surface of the passivation film to encompass the pixel hole, to form a border with the passivation film and having a thickness that decreases as it goes up the side surface of the passivation film.

Abstract: A liquid crystal display device according to the present invention includes a gate line on a substrate; a data line crossing the gate line with a gate insulating film to define a pixel area; a thin film transistor connected to the gate line and the data line; a semiconductor pattern overlapped along the data line; a double layer passivation film covering the data line and the thin film transistor, wherein layers of the passivation film have different etching rates; and a pixel electrode formed in a pixel hole penetrating an upper passivation film of the double layer passivation film and connected to a drain electrode of the thin film transistor exposed through a drain contact hole, the pixel electrode forming a border with the upper passivation film surrounding the pixel hole.