Abstract: An electronic device includes a host processor configured to: convert a sparse matrix compressed and expressed in a first compressed format into a second compressed storage format, based on a feature of the sparse matrix; preprocess a vector based on the second compressed storage format; and transmit the sparse matrix converted into the second compressed storage format and the preprocessed vector to a computing device; and the computing device configured to multiply the sparse matrix converted into the second compressed storage format by the preprocessed vector.

Abstract: A method of performing a floating-point operation using a memory processor (the floating-point operation being a multiplication of a first matrix and a second matrix that are double-precision floating-point matrices) includes: determining whether an emulation is to be used to perform the floating-point operation, based on a result of the determining whether the emulation is to be used, determining whether to use the memory processor for the emulation, the emulation comprising stages, based on a result of the determining whether to use the memory processor for the emulation, individually determining whether to use the memory processor for each stage of the emulation, and multiplying the first matrix and the second matrix based on a result of the individually determining whether to use the memory processor.