Patents by Inventor Jinrong HUANG
Jinrong HUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250201965Abstract: A thermal management system includes a compressor, a first heat exchanger, and a heat exchange assembly. An exhaust port of the compressor is connected to the heat exchange assembly, a first port of the first heat exchanger is connected to an air inlet of the compressor, and a second port of the first heat exchanger is connected to the heat exchange assembly. The heat exchange assembly includes a first heat exchange plate and a second heat exchange plate which are disposed in parallel, and each of the first heat exchange plate and the second heat exchange plate is configured for adjusting the temperature of a battery module.Type: ApplicationFiled: March 7, 2025Publication date: June 19, 2025Inventors: Chunfen WU, Jingke ZHANG, Shanling GAO, Yinhui DING, Jinrong HUANG
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Patent number: 12100680Abstract: A semiconductor structure includes: a first base having a first face, a second base having a second face and a welded structure. The first base is provided with an electrical connection column protruding from the first face. A conductive column is provided in the second base, and a first groove and a second groove are further provided at the second face. The first groove is located above the conductive column, and the second groove exposes at least part of a side surface of the conductive column. The protruding portion of the electrical connection column is located in the second groove, and part of a side surface of the electrical connection column and part of the side surface of the conductive column overlap in staggered way in a direction perpendicular to the first face or the second surface. At least part of the welded structure is filled in the first groove.Type: GrantFiled: June 22, 2022Date of Patent: September 24, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Luguang Wang, Jinrong Huang
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Patent number: 12092654Abstract: The present disclosure discloses an assembly for carrying a chip, and a device and a method for testing a chip. The assembly for carrying a chip is configured to fasten chips of different sizes, and includes a rotatable vertical rod, a cross beam, a first sidewall, and a second sidewall. The rotatable vertical rod is provided with a gear that surrounds the rotatable vertical rod with gear teeth. The cross beam is internally provided with a first through hole and a first chute. A top of the first sidewall is connected to a first connecting rod located in the first chute. A top of the second sidewall is connected to a second connecting rod located in the first chute. A side surface of the first connecting rod is provided with a plurality of first tooth grooves arranged linearly.Type: GrantFiled: May 18, 2022Date of Patent: September 17, 2024Assignee: Changxin Memory Technologies, Inc.Inventor: Jinrong Huang
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Patent number: 11874324Abstract: The present disclosure relates to a device for carrying a chip, and a device and a method for testing a chip. The device for carrying a chip is configured to fasten chips of different sizes, and includes a support box and a plurality of first elastic snap rings. The support box is configured to carry a chip. A first connection terminal of the first elastic snap ring is provided on a first inner side wall of the support box, a second connection terminal of the first elastic snap ring is suspended, and is configured to be in contact with the chip and provide a pressure in a first direction for the chip because an elastic body of the first elastic snap ring is in an elastically compressed state.Type: GrantFiled: January 20, 2022Date of Patent: January 16, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Jinrong Huang
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Patent number: 11815546Abstract: Embodiments of the present application disclose a fixing device and fixing method for chip test and a chip tester. The fixing device for chip test includes: a carrier with a fixing chamber for fixing a chip formed inside, a plurality of adjustors being disposed on sidewalls of the fixing chamber and configured to be extended or retracted to adjust a position of the chip in two orthogonal directions within a horizontal plane; and a top cover configured to cooperate with the carrier to fix the chip in a vertical direction, wherein at least one adjustable pressing cover is disposed at a bottom of the top cover, so as to autonomously adjust a pressing force applied to the chip by the pressing cover in the vertical direction. The present application is suitable for fixing chips with various overall dimensions, and can adaptively adjust a pressing force.Type: GrantFiled: October 18, 2021Date of Patent: November 14, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Jinrong Huang
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Publication number: 20230238346Abstract: A semiconductor structure includes: a first base having a first face, a second base having a second face and a welded structure. The first base is provided with an electrical connection column protruding from the first face. A conductive column is provided in the second base, and a first groove and a second groove are further provided at the second face. The first groove is located above the conductive column, and the second groove exposes at least part of a side surface of the conductive column. The protruding portion of the electrical connection column is located in the second groove, and part of a side surface of the electrical connection column and part of the side surface of the conductive column overlap in staggered way in a direction perpendicular to the first face or the second surface. At least part of the welded structure is filled in the first groove.Type: ApplicationFiled: June 22, 2022Publication date: July 27, 2023Inventors: Luguang WANG, Jinrong HUANG
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Publication number: 20230231039Abstract: Embodiments disclose a semiconductor structure and a method for fabricating the same. The semiconductor structure includes: a substrate, a gate dielectric layer, a first conductive layer, and a conductive plug. The gate dielectric layer is provided on the substrate, and the first conductive layer is provided on the gate dielectric layer. The conductive plug is provided on the gate dielectric layer and covers a side wall of the first conductive layer, where a projection of the conductive plug on the substrate and a projection of the gate dielectric layer on the substrate at least partially overlap. By providing the conductive plug, a breakdown current can break down a region of the gate dielectric layer corresponding to the conductive plug by means of the conductive plug. That is, a breakdown position is adjusted by controlling an overlapping position between the conductive plug and the gate dielectric layer.Type: ApplicationFiled: January 4, 2023Publication date: July 20, 2023Inventor: Jinrong HUANG
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Publication number: 20230223371Abstract: A semiconductor structure and a method for manufacturing a semiconductor structure are provided. The semiconductor structure includes: a first base with a first surface, in which a conductive pillar is arranged in the first base, the first surface includes a first groove, and the first groove exposes a top surface and a portion of a sidewall of the conductive pillar; a second base with a second surface, in which the first surface is bonded to the second surface, the second surface includes a second groove, an electrical connection pillar is arranged in the second base, the electrical connection pillar is located in the second groove, and the electrical connection pillar protrudes from the second surface; and an electrical connection structure, in which the electrical connection structure and a portion of the electrical connection pillar are embedded into the first groove.Type: ApplicationFiled: June 22, 2022Publication date: July 13, 2023Inventors: Luguang WANG, Jinrong HUANG
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Publication number: 20230003789Abstract: Embodiments of the present application disclose a fixing device and fixing method for chip test and a chip tester. The fixing device for chip test includes: a carrier with a fixing chamber for fixing a chip formed inside, a plurality of adjustors being disposed on sidewalls of the fixing chamber and configured to be extended or retracted to adjust a position of the chip in two orthogonal directions within a horizontal plane; and a top cover configured to cooperate with the carrier to fix the chip in a vertical direction, wherein at least one adjustable pressing cover is disposed at a bottom of the top cover, so as to autonomously adjust a pressing force applied to the chip by the pressing cover in the vertical direction. The present application is suitable for fixing chips with various overall dimensions, and can adaptively adjust a pressing force.Type: ApplicationFiled: October 18, 2021Publication date: January 5, 2023Inventor: Jinrong HUANG
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Publication number: 20230003763Abstract: The present disclosure discloses an assembly for carrying a chip, and a device and a method for testing a chip. The assembly for carrying a chip is configured to fasten chips of different sizes, and includes a rotatable vertical rod, a cross beam, a first sidewall, and a second sidewall. The rotatable vertical rod is provided with a gear that surrounds the rotatable vertical rod with gear teeth. The cross beam is internally provided with a first through hole and a first chute. A top of the first sidewall is connected to a first connecting rod located in the first chute. A top of the second sidewall is connected to a second connecting rod located in the first chute. A side surface of the first connecting rod is provided with a plurality of first tooth grooves arranged linearly.Type: ApplicationFiled: May 18, 2022Publication date: January 5, 2023Inventor: Jinrong Huang
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Publication number: 20230003792Abstract: The present disclosure relates to a device for carrying a chip, and a device and a method for testing a chip. The device for carrying a chip is configured to fasten chips of different sizes, and includes a support box and a plurality of first elastic snap rings. The support box is configured to carry a chip. A first connection terminal of the first elastic snap ring is provided on a first inner side wall of the support box, a second connection terminal of the first elastic snap ring is suspended, and is configured to be in contact with the chip and provide a pressure in a first direction for the chip because an elastic body of the first elastic snap ring is in an elastically compressed state.Type: ApplicationFiled: January 20, 2022Publication date: January 5, 2023Inventor: Jinrong HUANG
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Publication number: 20200390130Abstract: The disclosure herein discloses a processing method of soaking-free mixed beans, and belongs to the technical field of deep processing of grains. By performing a combination of water supplementing and high-temperature fluidization processing on the mixed beans, embryos of the mixed beans slightly crack from one side by a width of 0.Type: ApplicationFiled: August 24, 2020Publication date: December 17, 2020Inventors: Yongfu LI, Min JIE, Feng SHI, Jinrong HUANG, Siyu HUANG, Zhengxing CHEN
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Publication number: 20200359664Abstract: The disclosure discloses delicious low-glycemic index formula rice and its application, and belongs to the technical field of food. The low-GI formula rice comprises low-GI rice, rice and coarse cereals; the mass ratio of the low-GI rice to the rice to the coarse cereals is (3-5):(0-2):5; and the coarse cereals comprise 15-25 parts of mung beans, 8-15 parts of black rice, 10-15 parts of oat milled rice with embryo, 5-10 parts of black sticky rice and 3-10 parts of tartary buckwheat.Type: ApplicationFiled: August 4, 2020Publication date: November 19, 2020Inventors: Yongfu LI, Jinrong HUANG, Feng SHI, Zhengxing CHEN