Abstract: An embodiment rotor includes a stacked core including stacked lamination sheets. The lamination sheets include lamination segments arranged in a circle, the stacked core has an upper layer lamination segment coupled to a lower layer lamination segment with a phase difference therebetween of a first angle with respect to a center of the stacked core, the stacked lamination segments have keys arranged in a straight line on an inner surface of the stacked core so that the keys are inserted into a key way disposed in a motor shaft in an axial direction, the lamination segments have a substantially identical shape and are arranged with an interval of a second angle with respect to a center of the rotor thus having a substantially identical pattern, and the lamination segments include upper and lower layer coupling portions repeatedly disposed at intervals of the second angle in a circumferential direction.

Abstract: The present invention relates to a cover that is used as a backrest cover in daily use and also as a life jacket in an emergency. More particularly, the present invention relates to a backrest cover including: a front portion configured to cover a front surface of the backrest; a rear portion configured to cover a rear surface of the backrest; a connector configured to extend across an upper end of the backrest, connecting the front and back portions; and a buoyancy body provided in at least one of the front portion, the rear portion, and the connector.

Abstract: The present invention relates to a cover that is used as a backrest cover in daily use and also as a life jacket in an emergency. More particularly, the present invention relates to a backrest cover including: a front portion configured to cover a front surface of the backrest; a rear portion configured to cover a rear surface of the backrest; a connector configured to extend across an upper end of the backrest, connecting the front and back portions; and a buoyancy body provided in at least one of the front portion, the rear portion, and the connector.

Abstract: System on chip devices and methods of operating the system on chip devices are provided. An example method includes: setting a first characteristic by analyzing a request for allocation of a buffer memory of the system on chip device; allocating a first region of the buffer memory in response to the request for allocation of the buffer memory; and compressing or not compressing data provided to the first region, used on the first characteristic.

Abstract: A bus interface device for requesting and receiving data from a memory controller connected to a bus includes a request buffer and a request merger. The request buffer is configured to store a first data request signal for requesting first data and a second data request signal for requesting second data. The request merger is configured to determine whether to merge the first and second data request signals, and transmit a merged request signal for requesting the first data and the second data from the memory controller to the bus upon determining that the first and second data request signals are to be merged.

Abstract: System on chip devices and methods of operating the system on chip devices are provided. An example method includes: setting a first characteristic by analyzing a request for allocation of a buffer memory of the system on chip device; allocating a first region of the buffer memory in response to the request for allocation of the buffer memory; and compressing or not compressing data provided to the first region, used on the first characteristic.

Abstract: A bus interface device for requesting and receiving data from a memory controller connected to a bus includes a request buffer and a request merger. The request buffer is configured to store a first data request signal for requesting first data and a second data request signal for requesting second data. The request merger is configured to determine whether to merge the first and second data request signals, and transmit a merged request signal for requesting the first data and the second data from the memory controller to the bus upon determining that the first and second data request signals are to be merged.

Abstract: An apparatus and method for packet routing in a high-speed packet routing system. The apparatus includes an input unit and a control unit. The input unit temporarily stores an input packet and outputs the temporarily stored input packet to an output port determined by a previous router. The control unit determines an output port of a next router for the input packet.