Patents by Inventor Jinsheng Wei

Jinsheng Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240116655
    Abstract: Disclosed are a system and a method for capturing a space target. The system includes a plurality of capturing devices, a delivery device, a launching device, and a deceleration and recovery device, each of the plurality of capturing devices is configured to be launched into a target orbit to capture a defunct space target, the delivery device is configured to deliver, along a preset delivery trajectory, each of the plurality of capturing devices to a first preset location in the launching device, the launching device is configured to launch each of the plurality of capturing devices located at the first preset location into the target orbit to capture the defunct space target, and the deceleration and recovery device is configured to decelerate each of the plurality of capturing devices after it is launched and flies a preset distance.
    Type: Application
    Filed: December 20, 2023
    Publication date: April 11, 2024
    Applicant: Harbin Institute of Technology
    Inventors: Jinsheng GUO, Fan WU, Shi QIU, Jian CHEN, Cheng WEI, Hongxu WANG
  • Publication number: 20240101686
    Abstract: An EGFR nanobody, and a preparation method therefor and the use thereof. The EGFR nanobody has high affinity for a wild-type EGRF protein, and also recognizes the EGRFvIII protein.
    Type: Application
    Filed: December 8, 2021
    Publication date: March 28, 2024
    Inventors: Peipei Wei, Cuiqing Yang, Zhuoxiao Cao, Renhong Tang, Jinsheng Ren
  • Patent number: 10910957
    Abstract: The present disclosure involves a two stage inverter, a system for electrical power conversation, and a method of converting electrical power using silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs). One example implementation includes using two or more SiC MOSFETs in series with each MOSFET having a gate terminal for triggering a state switch between an on (conducting) and off (non-conducting) state of the MOSFET. An AC terminal is connected between the series SiC MOSFETS, and the series SiC MOSFETs are connected across a DC bus and in parallel with one or more capacitors.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: February 2, 2021
    Assignee: Calnetix Technologies, LLC
    Inventors: Suratkal P. Shenoy, Jinsheng Wei, Octavio Solis
  • Patent number: 10225908
    Abstract: An active damping circuit is disclosed, which includes a peak current limiter, a drain source voltage limiter, a turn-on driver, a resistor shunt circuit, and a peak current sensor. The peak current sensor detects a rising edge of an input voltage from a phase cut dimmer by detecting a higher peak current. This drives a collector voltage of a second transistor of the peak current limiter low, which lowers a gate voltage of a first transistor of the peak current sensor, and forces it into a linear operating region, so it functions as a damping resistor. When the peak current sensor detects a decreased peak current, such that the turn-on edge of the input voltage is passed, the second transistor turns off, and the turn-on driver turns the first transistor on, such that the active damping circuit is waiting for a next edge of the input voltage.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: March 5, 2019
    Assignee: OSRAM SYLVANIA Inc.
    Inventors: Jinsheng Wei, Andrew Johnsen, Ranjit Jayabalan, Nitin Kumar
  • Patent number: 9992846
    Abstract: An active damping circuit and system including the same are disclosed. The active damping circuit includes a first resistor, a second resistor, a third resistor, a first transistor, a second transistor, a capacitor, and a microcontroller. The first resistor is connected to a base of the first transistor, and to the microcontroller output. The second resistor is connected to a positive voltage, and to a collector of the first transistor and a gate of the second transistor. The third resistor is connected to a logic ground, and to a source of the second transistor. The capacitor is connected to the collector of the first transistor, the second resistor, and the gate of the second transistor. A drain of the second transistor, and the first capacitor, and the second capacitor, and the microcontroller output, are also connected to the logic ground. An emitter of the first transistor is connected to ground.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: June 5, 2018
    Assignee: OSRAM SYLVANIA Inc.
    Inventors: Jinsheng Wei, Andrew Johnsen, Ranjit Jayabalan, Nitin Kumar
  • Publication number: 20180098395
    Abstract: An active damping circuit is disclosed, which includes a peak current limiter, a drain source voltage limiter, a turn-on driver, a resistor shunt circuit, and a peak current sensor. The peak current sensor detects a rising edge of an input voltage from a phase cut dimmer by detecting a higher peak current. This drives a collector voltage of a second transistor of the peak current limiter low, which lowers a gate voltage of a first transistor of the peak current sensor, and forces it into a linear operating region, so it functions as a damping resistor. When the peak current sensor detects a decreased peak current, such that the turn-on edge of the input voltage is passed, the second transistor turns off, and the turn-on driver turns the first transistor on, such that the active damping circuit is waiting for a next edge of the input voltage.
    Type: Application
    Filed: February 25, 2016
    Publication date: April 5, 2018
    Applicant: OSRAM SYLVANIA Inc.
    Inventors: Jinsheng Wei, Andrew Johnsen, Ranjit Jayabalan, Nitin Kumar
  • Publication number: 20180042084
    Abstract: An active damping circuit and system including the same are disclosed. The active damping circuit includes a first resistor, a second resistor, a third resistor, a first transistor, a second transistor, a capacitor, and a microcontroller. The first resistor is connected to a base of the first transistor, and to the microcontroller output. The second resistor is connected to a positive voltage, and to a collector of the first transistor and a gate of the second transistor. The third resistor is connected to a logic ground, and to a source of the second transistor. The capacitor is connected to the collector of the first transistor, the second resistor, and the gate of the second transistor. A drain of the second transistor, and the first capacitor, and the second capacitor, and the microcontroller output, are also connected to the logic ground. An emitter of the first transistor is connected to ground.
    Type: Application
    Filed: February 25, 2016
    Publication date: February 8, 2018
    Applicant: OSRAM SYLVANIA Inc.
    Inventors: Jinsheng Wei, Andrew Johnsen, Ranjit Jayabalan, Nitin Kumar