Patents by Inventor Jinshu Zhang

Jinshu Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9136157
    Abstract: A disclosed method for fabricating a structure in a semiconductor die comprises steps of implanting a deep N well in a substrate, depositing an epitaxial layer over the substrate, and forming a P well and a lateral isolation N well over the deep N well, wherein the lateral isolation N well and the P well are fabricated in the substrate and the epitaxial layer, and wherein the lateral isolation N well laterally surrounds the P well, and wherein the deep N well and the lateral isolation N well electrically isolate the P well. Implanting a deep N well can comprise steps of depositing a screen oxide layer over the substrate, forming a mask over the screen oxide layer, implanting the deep N well in the substrate, removing the mask, and removing the screen oxide layer. Depositing the epitaxial layer can comprise depositing a single crystal silicon over the substrate.
    Type: Grant
    Filed: August 5, 2005
    Date of Patent: September 15, 2015
    Assignee: Newport Fab, LLC
    Inventors: Arjun Kar-Roy, Marco Racanelli, Jinshu Zhang
  • Patent number: 8110888
    Abstract: High voltage semiconductor devices with high-voltage termination structures are constructed on lightly doped substrates. Lightly doped p-type substrates are particularly prone to depletion and inversion from positive charges, degrading the ability of associated termination structures to block high voltages. To improve the efficiency and stability of termination structures, second termination regions of the same dopant type as the substrate, more heavily doped than the substrate but more lightly doped than first termination regions, are positioned adjoining the first termination regions. The second termination regions raise the field threshold voltage where the surface is vulnerable and render the termination structure substantially insensitive to positive charges at the surface. The use of higher dopant concentration in the gap region without causing premature avalanche is facilitated by only creating second termination regions for regions lacking field plate protection.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: February 7, 2012
    Assignee: Microsemi Corporation
    Inventors: Jinshu Zhang, Dumitru Sdrulla, Dah Wen Tsang
  • Publication number: 20090072340
    Abstract: High voltage semiconductor devices with high-voltage termination structures are constructed on lightly doped substrates. Lightly doped p-type substrates are particularly prone to depletion and inversion from positive charges, degrading the ability of associated termination structures to block high voltages. To improve the efficiency and stability of termination structures, second termination regions of the same dopant type as the substrate, more heavily doped than the substrate but more lightly doped than first termination regions, are positioned adjoining the first termination regions. The second termination regions raise the field threshold voltage where the surface is vulnerable and render the termination structure substantially insensitive to positive charges at the surface. The use of higher dopant concentration in the gap region without causing premature avalanche is facilitated by only creating second termination regions for regions lacking field plate protection.
    Type: Application
    Filed: September 9, 2008
    Publication date: March 19, 2009
    Applicant: MICROSEMI CORPORATION
    Inventors: Jinshu Zhang, Dumitru Sdrulla, Dah Wen Tsang
  • Patent number: 7052966
    Abstract: A disclosed method for fabricating a structure in a semiconductor die comprises steps of implanting a deep N well in a substrate, depositing an epitaxial layer over the substrate, and forming a P well and a lateral isolation N well over the deep N well, wherein the lateral isolation N well and the P well are fabricated in the substrate and the epitaxial layer, and wherein the lateral isolation N well laterally surrounds the P well, and wherein the deep N well and the lateral isolation N well electrically isolate the P well. Implanting a deep N well can comprise steps of depositing a screen oxide layer over the substrate, forming a mask over the screen oxide layer, implanting the deep N well in the substrate, removing the mask, and removing the screen oxide layer. Depositing the epitaxial layer can comprise depositing a single crystal silicon over the substrate.
    Type: Grant
    Filed: April 9, 2003
    Date of Patent: May 30, 2006
    Assignee: Newport Fab, LLC
    Inventors: Arjun Kar-Roy, Marco Racanelli, Jinshu Zhang
  • Publication number: 20040201065
    Abstract: A disclosed method for fabricating a structure in a semiconductor die comprises steps of implanting a deep N well in a substrate, depositing an epitaxial layer over the substrate, and forming a P well and a lateral isolation N well over the deep N well, wherein the lateral isolation N well and the P well are fabricated in the substrate and the epitaxial layer, and wherein the lateral isolation N well laterally surrounds the P well, and wherein the deep N well and the lateral isolation N well electrically isolate the P well. Implanting a deep N well can comprise steps of depositing a screen oxide layer over the substrate, forming a mask over the screen oxide layer, implanting the deep N well in the substrate, removing the mask, and removing the screen oxide layer. Depositing the epitaxial layer can comprise depositing a single crystal silicon over the substrate.
    Type: Application
    Filed: April 9, 2003
    Publication date: October 14, 2004
    Applicant: Newport Fab,LLC dba Jazz Semiconductor
    Inventors: Arjun Kar-Roy, Marco Racanelli, Jinshu Zhang