Abstract: A non-volatile memory device includes a first stack includes first conductive patterns and firs t dielectric layers that are alternately stacked in a first direction on a source structure, a second stack includes second conductive patterns and second dielectric layers that are alternately stacked in the first direction on the first stack opposite the source structure, a first channel structure extending into the first stack in the first direction, and a second channel structure extending into the second stack in the first direction and being on the first channel structure, a top of the first channel structure being oppo site the source structure and is in contact with a bottom of the second channel structure, and a width of the top of the first channel structure being smaller than a width of the bottom of the second channel structure.

Abstract: A non-volatile memory device and a non-volatile memory system comprising the same are provided. The non-volatile memory device includes a first stack in which a first conductive pattern and a first dielectric layer are alternately stacked in a first direction on a substrate, a second stack in which a second conductive pattern and a second dielectric layer are alternately stacked in the first direction on the first stack opposite the substrate, a first monitoring channel structure that penetrates the first stack in the first direction, and a second monitoring channel structure that penetrates the second stack in the first direction and is on the first monitoring channel structure. A width of a top of the first monitoring channel structure opposite the substrate is smaller than a width of a bottom of the second monitoring channel structure adjacent the top of the first monitoring channel structure.

Abstract: A non-volatile memory device and a non-volatile memory system comprising the same are provided. The non-volatile memory device includes a first stack in which a first conductive pattern and a first dielectric layer are alternately stacked in a first direction on a substrate, a second stack in which a second conductive pattern and a second dielectric layer are alternately stacked in the first direction on the first stack opposite the substrate, a first monitoring channel structure that penetrates the first stack in the first direction, and a second monitoring channel structure that penetrates the second stack in the first direction and is =on the first monitoring channel structure. A width of a top of the first monitoring channel structure opposite the substrate is smaller than a width of a bottom of the second monitoring channel structure adjacent the top of the first monitoring channel structure.

Abstract: A semiconductor device may include gate structures spaced apart above a top surface of a substrate. The gate structures may include a horizontal electrode extending in a first direction parallel with the top surface of a substrate. An isolation insulating layer may be disposed between the gate structures. A plurality of cell pillars may penetrate the horizontal electrode and connect to the substrate. The plurality of cell pillars may include a minimum spacing defined by a shortest distance between any two of the plurality of cell pillars. The thickness of the horizontal electrode may be greater than the minimum spacing of the cell pillars.

Abstract: A method of manufacturing a three-dimensional semiconductor memory device comprises forming a thin layer structure by alternately stacking first and second material layers on a substrate, forming a penetration dent penetrating the thin layer structure and exposing a top surface of the substrate recessed by the penetration dent, forming a vertical insulation layer penetrating the thin layer structure to cover an inner wall of the penetration dent, forming a semiconductor pattern penetrating the vertical insulation layer at the penetration dent to be inserted into the substrate, and forming an oxide layer between the thin layer structure and the substrate by oxidizing a sidewall of the penetration dent.

Abstract: A vertical type semiconductor device includes a pillar structure protruding from a top surface of a substrate of a cell array region. Word lines extend while surrounding the pillar structure. Word line contacts contact edges of the word lines functioning as pad portions. An insulating interlayer pattern is provided on the substrate of a peripheral circuit region, which is disposed at an outer peripheral portion of the cell array region. A first contact plug contacts the substrate of the peripheral circuit region. A second contact plug contacts a top surface of the first contact plug and has a top surface aligned on the same plane with the top surfaces of the word line contacts. The first and second contact plugs are stacked in the peripheral circuit region, so the failure of the vertical type semiconductor device is reduced.

Abstract: Three-dimensional semiconductor devices are provided. The three-dimensional semiconductor device includes a substrate, a buffer layer on the substrate. The buffer layer includes a material having an etching selectivity relative to that of the substrate. A multi-layer stack including alternating insulation patterns and conductive patterns is provided on the buffer layer opposite the substrate. One or more active patterns respectively extend through the alternating insulation patterns and conductive patterns of the multi-layer stack and into the buffer layer. Related fabrication methods are also discussed.

Abstract: Methods of manufacturing vertical semiconductor devices may include forming a mold structure including sacrificial layers and insulating interlayers with a first opening formed therethrough. The sacrificial layers and the insulating interlayers may be stacked repeatedly and alternately on a substrate. The first opening may expose the substrate. Blocking layers may be formed by oxidizing portions of the sacrificial layers exposed by the first opening. A first semiconductor layer pattern, a charge trapping layer pattern and a tunnel insulation layer pattern, respectively, may be formed on the sidewall of the first opening. A second semiconductor layer may be formed on the first polysilicon layer pattern and the bottom of the first opening. The sacrificial layers and the insulating interlayers may be partially removed to form a second opening. The sacrificial layers may be removed to form grooves between the insulating interlayers. Control gate electrodes may be formed in the grooves.

Abstract: A method of manufacturing a three-dimensional semiconductor memory device comprises forming a thin layer structure by alternately stacking first and second material layers on a substrate, forming a penetration dent penetrating the thin layer structure and exposing a top surface of the substrate recessed by the penetration dent, forming a vertical insulation layer penetrating the thin layer structure to cover an inner wall of the penetration dent, forming a semiconductor pattern penetrating the vertical insulation layer at the penetration dent to be inserted into the substrate, and forming an oxide layer between the thin layer structure and the substrate by oxidizing a sidewall of the penetration dent.

Abstract: The present invention relates to an organic electroluminescence device containing a light emitting metallic compound of Chemical Formula 1. In the Chemical Formula 1, M is selected from Ir, Pt, Rh, Re, and Os, and m is 2, provided that m is 1 when M is Pt.

Abstract: Three-dimensional semiconductor devices are provided. The three-dimensional semiconductor device includes a substrate, a buffer layer on the substrate. The buffer layer includes a material having an etching selectivity relative to that of the substrate. A multi-layer stack including alternating insulation patterns and conductive patterns is provided on the buffer layer opposite the substrate. One or more active patterns respectively extend through the alternating insulation patterns and conductive patterns of the multi-layer stack and into the buffer layer. Related fabrication methods are also discussed.

Abstract: A semiconductor device may include gate structures spaced apart above a top surface of a substrate. The gate structures may include a horizontal electrode extending in a first direction parallel with the top surface of a substrate. An isolation insulating layer may be disposed between the gate structures. A plurality of cell pillars may penetrate the horizontal electrode and connect to the substrate. The plurality of cell pillars may include a minimum spacing defined by a shortest distance between any two of the plurality of cell pillars. The thickness of the horizontal electrode may be greater than the minimum spacing of the cell pillars.

Abstract: A vertical structure nonvolatile memory device can include a channel layer that extends in a vertical direction on a substrate. A memory cell string includes a plurality of transistors that are disposed on the substrate in the vertical direction along a vertical sidewall of the channel layer. At least one of the plurality of transistors includes at least one recess in a gate of the transistor into which at least one protrusion, which includes the channel layer, extends.

Abstract: Three-dimensional semiconductor devices are provided. The three-dimensional semiconductor device includes a substrate, a buffer layer on the substrate. The buffer layer includes a material having an etching selectivity relative to that of the substrate. A multi-layer stack including alternating insulation patterns and conductive patterns is provided on the buffer layer opposite the substrate. One or more active patterns respectively extend through the alternating insulation patterns and conductive patterns of the multi-layer stack and into the buffer layer. Related fabrication methods are also discussed.

Abstract: A three dimensional semiconductor memory device includes an electrode structure having a plurality of conductive electrode patterns and insulating patterns alternatingly stacked on a substrate. Opposite sidewalls of the electrode structure include respective grooves therein extending in a direction substantially perpendicular to the substrate. First and second active patterns protrude from the substrate and extend within the grooves in the opposite sidewalls of the electrode structure, respectively. Respective data storing layers extend in the grooves between the conductive electrode patterns of the electrode structure and sidewalls of the first and second active patterns adjacent thereto. Related fabrication methods are also discussed.

Abstract: Methods of manufacturing vertical semiconductor devices may include forming a mold structure including sacrificial layers and insulating interlayers with a first opening formed therethrough. The sacrificial layers and the insulating interlayers may be stacked repeatedly and alternately on a substrate. The first opening may expose the substrate. Blocking layers may be formed by oxidizing portions of the sacrificial layers exposed by the first opening. A first semiconductor layer pattern, a charge trapping layer pattern and a tunnel insulation layer pattern, respectively, may be formed on the sidewall of the first opening. A second semiconductor layer may be formed on the first polysilicon layer pattern and the bottom of the first opening. The sacrificial layers and the insulating interlayers may be partially removed to form a second opening. The sacrificial layers may be removed to form grooves between the insulating interlayers. Control gate electrodes may be formed in the grooves.

Abstract: Methods of manufacturing vertical semiconductor devices may include forming a mold structure including sacrificial layers and insulating interlayers with a first opening formed therethrough. The sacrificial layers and the insulating interlayers may be stacked repeatedly and alternately on a substrate. The first opening may expose the substrate. Blocking layers may be formed by oxidizing portions of the sacrificial layers exposed by the first opening. A first semiconductor layer pattern, a charge trapping layer pattern and a tunnel insulation layer pattern, respectively, may be formed on the sidewall of the first opening. A second semiconductor layer may be formed on the first polysilicon layer pattern and the bottom of the first opening. The sacrificial layers and the insulating interlayers may be partially removed to form a second opening. The sacrificial layers may be removed to form grooves between the insulating interlayers. Control gate electrodes may be formed in the grooves.

Abstract: A vertical structure nonvolatile memory device can include a channel layer that extends in a vertical direction on a substrate. A memory cell string includes a plurality of transistors that are disposed on the substrate in the vertical direction along a vertical sidewall of the channel layer. At least one of the plurality of transistors includes at least one recess in a gate of the transistor into which at least one protrusion, which includes the channel layer, extends.

Abstract: A vertical type semiconductor device includes a pillar structure protruding from a top surface of a substrate of a cell array region. Word lines extend while surrounding the pillar structure. Word line contacts contact edges of the word lines functioning as pad portions. An insulating interlayer pattern is provided on the substrate of a peripheral circuit region, which is disposed at an outer peripheral portion of the cell array region. A first contact plug contacts the substrate of the peripheral circuit region. A second contact plug contacts a top surface of the first contact plug and has a top surface aligned on the same plane with the top surfaces of the word line contacts. The first and second contact plugs are stacked in the peripheral circuit region, so the failure of the vertical type semiconductor device is reduced.

Abstract: Three-dimensional semiconductor devices are provided. The three-dimensional semiconductor device includes a substrate, a buffer layer on the substrate. The buffer layer includes a material having an etching selectivity relative to that of the substrate. A multi-layer stack including alternating insulation patterns and conductive patterns is provided on the buffer layer opposite the substrate. One or more active patterns respectively extend through the alternating insulation patterns and conductive patterns of the multi-layer stack and into the buffer layer. Related fabrication methods are also discussed.