Patents by Inventor Jin-Tae Noh
Jin-Tae Noh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240104115Abstract: Disclosed herein are a method and apparatus for converting a credential data schema.Type: ApplicationFiled: July 11, 2023Publication date: March 28, 2024Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Seok-Hyun KIM, Soo-Hyung KIM, Young-Seob CHO, Geon-Woo KIM, Young-Sam KIM, Jong-Hyouk NOH, Kwan-Tae CHO, Sang-Rae CHO, Jin-Man CHO, Seung-Hun JIN
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Publication number: 20240104990Abstract: Disclosed herein is a method for user-centered visitor access management, which may include issuing, by a management office server, a digital certificate to a householder terminal; registering, by a wall-pad, a householder in response to a request to register the householder based on the digital certificate; requesting, by the householder terminal, the management office server to register a visitor based on a visit request from a visitor terminal and delegating the digital certificate to the visitor terminal; making an entry request to a management terminal based on the digital certificate; verifying, by the wall-pad, the digital certificate based on a request for verification for entry from a wall-pad management terminal and providing a verification result to the wall-pad management terminal when the management terminal is the wall-pad management terminal; and managing and controlling, by the wall-pad, permission to use home devices based on delegated permission information of the digital certificate.Type: ApplicationFiled: March 22, 2023Publication date: March 28, 2024Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Seok-Hyun KIM, Young-Seob CHO, Soo-Hyung KIM, Geon-Woo KIM, Young-Sam KIM, Jong-Hyouk NOH, Kwan-Tae CHO, Sang-Rae CHO, Jin-Man CHO, Seung-Hun JIN
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Patent number: 10600806Abstract: A stack structure includes conductive layer patterns and interlayer insulating layer patterns alternately stacked on one another. A channel hole penetrates the stack structure. A dielectric layer is disposed on a sidewall of the channel hole. A channel layer is disposed on the dielectric layer and in the channel hole. A passivation layer is disposed on the channel layer and in the channel hole. The channel layer is interposed between the passivation layer and the dielectric layer. An air gap is surrounded by the passivation layer. A width of the air gap is larger than a width of the passivation layer.Type: GrantFiled: July 1, 2019Date of Patent: March 24, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung Gil Kim, Seul Ye Kim, Hong Suk Kim, Jin Tae Noh, Ji Hoon Choi, Jae Young Ahn
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Publication number: 20190326321Abstract: A stack structure includes conductive layer patterns and interlayer insulating layer patterns alternately stacked on one another. A channel hole penetrates the stack structure. A dielectric layer is disposed on a sidewall of the channel hole. A channel layer is disposed on the dielectric layer and in the channel hole. A passivation layer is disposed on the channel layer and in the channel hole. The channel layer is interposed between the passivation layer and the dielectric layer. An air gap is surrounded by the passivation layer. A width of the air gap is larger than a width of the passivation layer.Type: ApplicationFiled: July 1, 2019Publication date: October 24, 2019Inventors: Sung Gil KIM, Seul Ye KIM, Hong Suk KIM, Jin Tae NOH, Ji Hoon CHOI, Jae Young AHN
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Patent number: 10340284Abstract: A stack structure includes conductive layer patterns and interlayer insulating layer patterns alternately stacked on one another. A channel hole penetrates the stack structure. A dielectric layer is disposed on a sidewall of the channel hole. A channel layer is disposed on the dielectric layer and in the channel hole. A passivation layer is disposed on the channel layer and in the channel hole. The channel layer is interposed between the passivation layer and the dielectric layer. An air gap is surrounded by the passivation layer. A width of the air gap is larger than a width of the passivation layer.Type: GrantFiled: January 14, 2018Date of Patent: July 2, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Sung Gil Kim, Seul Ye Kim, Hong Suk Kim, Jin Tae Noh, Ji Hoon Choi, Jae Young Ahn
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Publication number: 20190013328Abstract: A stack structure includes conductive layer patterns and interlayer insulating layer patterns alternately stacked on one another. A channel hole penetrates the stack structure. A dielectric layer is disposed on a sidewall of the channel hole. A channel layer is disposed on the dielectric layer and in the channel hole. A passivation layer is disposed on the channel layer and in the channel hole. The channel layer is interposed between the passivation layer and the dielectric layer. An air gap is surrounded by the passivation layer. A width of the air gap is larger than a width of the passivation layer.Type: ApplicationFiled: January 14, 2018Publication date: January 10, 2019Inventors: Sung Gil KIM, Seul Ye KIM, Hong Suk KIM, Jin Tae NOH, Ji Hoon CHOI, Jae Young AHN
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Patent number: 9530899Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes insulation layers and gate electrodes alternately stacked on a substrate, a vertical channel vertically passing through the insulation layers and the gate electrodes, and a threshold voltage controlling insulation layer, a tunnel insulation layer and a charge storage layer disposed between the vertical channel and the gate electrodes, wherein the threshold voltage controlling insulation layer is disposed between the charge storage layer and the vertical channel and including a material configured to suppress an inversion layer from being formed in the vertical channel.Type: GrantFiled: September 2, 2014Date of Patent: December 27, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Bi O Kim, Jin-Tae Noh, Su-Jin Shin, Jae-Young Ahn, Ki-Hyun Hwang
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Patent number: 9343546Abstract: A semiconductor device includes a channel region extending in a vertical direction perpendicular to a substrate and having a nitrogen concentration distribution, a plurality of gate electrodes arranged on a side wall of the channel region and separated from each other in a vertical direction, and a gate dielectric layer disposed between the channel region and the gate electrodes. The nitrogen concentration distribution has a first concentration near an interface between the channel region and the gate dielectric layer.Type: GrantFiled: October 3, 2014Date of Patent: May 17, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Bi-o Kim, Jin-tae Noh, Chang-woo Sun, Jae-young Ahn, Seung-hyun Lim, Ki-hyun Hwang
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Patent number: 9064895Abstract: Methods of fabricating vertical memory devices are provided including forming a plurality of alternating insulating layers and sacrificial layers on a substrate; patterning and etching the plurality of insulating layer and sacrificial layers to define an opening that exposes at least a portion of a surface of the substrate; forming a charge trapping pattern and a tunnel insulating pattern on a side wall of the opening; forming a channel layer on the tunnel insulating layer on the sidewall of the opening, the channel layer including N-type impurity doped polysilicon; forming a buried insulating pattern on the channel layer in the opening; and forming a blocking dielectric layer and a control gate on the charge trapping pattern of one side wall of the channel layer.Type: GrantFiled: July 17, 2013Date of Patent: June 23, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Bi-O Kim, Toshiro Nakanishi, Jin-Tae Noh, Chang-Woo Sun, Seung-Hyun Lim, Jae-Young Ahn, Ki-Hyun Hwang
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Publication number: 20150129954Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes insulation layers and gate electrodes alternately stacked on a substrate, a vertical channel vertically passing through the insulation layers and the gate electrodes, and a threshold voltage controlling insulation layer, a tunnel insulation layer and a charge storage layer disposed between the vertical channel and the gate electrodes, wherein the threshold voltage controlling insulation layer is disposed between the charge storage layer and the vertical channel and including a material configured to suppress an inversion layer from being formed in the vertical channel.Type: ApplicationFiled: September 2, 2014Publication date: May 14, 2015Inventors: Bi O. Kim, Jin-Tae Noh, Su-Jin Shin, Jae-Young Ahn, Ki-Hyun Hwang
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Publication number: 20150056797Abstract: A semiconductor device includes a channel region extending in a vertical direction perpendicular to a substrate and having a nitrogen concentration distribution, a plurality of gate electrodes arranged on a side wall of the channel region and separated from each other in a vertical direction, and a gate dielectric layer disposed between the channel region and the gate electrodes. The nitrogen concentration distribution has a first concentration near an interface between the channel region and the gate dielectric layer.Type: ApplicationFiled: October 3, 2014Publication date: February 26, 2015Inventors: Bi-o Kim, Jin-tae Noh, Chang-woo Sun, Jae-young Ahn, Seung-hyun Lim, Ki-hyun Hwang
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Patent number: 8901643Abstract: A semiconductor device includes a channel region extending in a vertical direction perpendicular to a substrate and having a nitrogen concentration distribution, a plurality of gate electrodes arranged on a side wall of the channel region and separated from each other in a vertical direction, and a gate dielectric layer disposed between the channel region and the gate electrodes. The nitrogen concentration distribution has a first concentration near an interface between the channel region and the gate dielectric layer.Type: GrantFiled: March 12, 2013Date of Patent: December 2, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Bi-o Kim, Jin-tae Noh, Chang-woo Sun, Jae-young Ahn, Seung-hyun Lim, Ki-hyun Hwang
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Publication number: 20140024189Abstract: Methods of fabricating vertical memory devices are provided including forming a plurality of alternating insulating layers and sacrificial layers on a substrate; patterning and etching the plurality of insulating layer and sacrificial layers to define an opening that exposes at least a portion of a surface of the substrate; forming a charge trapping pattern and a tunnel insulating pattern on a side wall of the opening; forming a channel layer on the tunnel insulating layer on the sidewall of the opening, the channel layer including N-type impurity doped polysilicon; forming a buried insulating pattern on the channel layer in the opening; and forming a blocking dielectric layer and a control gate on the charge trapping pattern of one side wall of the channel layer.Type: ApplicationFiled: July 17, 2013Publication date: January 23, 2014Inventors: Bi-O Kim, Toshiro Nakanishi, Jin-Tae Noh, Chang-Woo Sun, Seung-Hyun Lim, Jae-Young Ahn, Ki-Hyun Hwang
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Publication number: 20130270631Abstract: A semiconductor device includes a channel region extending in a vertical direction perpendicular to a substrate and having a nitrogen concentration distribution, a plurality of gate electrodes arranged on a side wall of the channel region and separated from each other in a vertical direction, and a gate dielectric layer disposed between the channel region and the gate electrodes. The nitrogen concentration distribution has a first concentration near an interface between the channel region and the gate dielectric layer.Type: ApplicationFiled: March 12, 2013Publication date: October 17, 2013Inventors: Bi-o KIM, Jin-tae NOH, Chang-woo SUN, Jae-young AHN, Seung-hyun LIM, Ki-hyun HWANG
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Patent number: 8445367Abstract: In a method of manufacturing a semiconductor device, a plurality of sacrificial layers and a plurality of insulating interlayers are repeatedly and alternately on a substrate. The insulating interlayers include a different material from a material of the sacrificial layers. At least one opening through the insulating interlayers and the sacrificial layers are formed. The at least one opening exposes the substrate. The seed layer is formed on an inner wall of the at least one opening using a first silicon source gas. A polysilicon channel is formed in the at least one opening by growing the seed layer. The sacrificial layers are removed to form a plurality of grooves between the insulating interlayers. A plurality of gate structures is formed in the grooves, respectively.Type: GrantFiled: November 2, 2011Date of Patent: May 21, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Tae Noh, Hun-Hyeong Lim, Ki-Hyun Hwang, Jin-Gyun Kim, Sang-Ryol Yang
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Patent number: 8330207Abstract: A flash memory device including a lower tunnel insulation layer on a substrate, an upper tunnel insulation layer on the lower tunnel insulation layer, and a P-type gate on the upper tunnel insulation layer, wherein the upper tunnel insulation layer includes an amorphous oxide layer.Type: GrantFiled: January 4, 2008Date of Patent: December 11, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-kweon Baek, Sang-ryol Yang, Si-young Choi, Bon-young Koo, Ki-hyun Hwang, Jin-tae Noh
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Patent number: 8227357Abstract: Methods of fabricating a silicon oxide layer using an inorganic silicon precursor and methods of fabricating a semiconductor device using the same are provided. The methods of fabricating a semiconductor device include forming a tunnel insulating layer and a charge storage layer on a substrate; forming a dielectric layer structure on the charge storage layer using an atomic layer deposition (ALD) method, the dielectric layer structure including a first dielectric layer formed of silicon oxide, a second dielectric layer on the first dielectric layer formed of a material different from the material forming the first dielectric layer, and a third dielectric layer formed of the silicon oxide on the second dielectric layer; and forming a control gate on the dielectric layer structure.Type: GrantFiled: March 24, 2010Date of Patent: July 24, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: In-Sun Yi, Ki-Hyun Hwang, Jin-Tae Noh, Jae-Young Ahn, Si-Young Choi
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Publication number: 20120115293Abstract: In a method of manufacturing a semiconductor device, a plurality of sacrificial layers and a plurality of insulating interlayers are repeatedly and alternately on a substrate. The insulating interlayers include a different material from a material of the sacrificial layers. At least one opening through the insulating interlayers and the sacrificial layers are formed. The at least one opening exposes the substrate. The seed layer is formed on an inner wall of the at least one opening using a first silicon source gas. A polysilicon channel is formed in the at least one opening by growing the seed layer. The sacrificial layers are removed to form a plurality of grooves between the insulating interlayers. A plurality of gate structures is formed in the grooves, respectively.Type: ApplicationFiled: November 2, 2011Publication date: May 10, 2012Inventors: Jin-Tae NOH, Hun-Hyeong Lim, Ki-Hyun Hwang, Jin-Gyun Kim, Sang-Ryol Yang
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Publication number: 20100248465Abstract: Methods of fabricating a silicon oxide layer using an inorganic silicon precursor and methods of fabricating a semiconductor device using the same are provided. The methods of fabricating a semiconductor device include forming a tunnel insulating layer and a charge storage layer on a substrate; forming a dielectric layer structure on the charge storage layer using an atomic layer deposition (ALD) method, the dielectric layer structure including a first dielectric layer formed of silicon oxide, a second dielectric layer on the first dielectric layer formed of a material different from the material forming the first dielectric layer, and a third dielectric layer formed of the silicon oxide on the second dielectric layer; and forming a control gate on the dielectric layer structure.Type: ApplicationFiled: March 24, 2010Publication date: September 30, 2010Inventors: In-Sun Yi, Ki-Hyun Hwang, Jin-Tae Noh, Jae-Young Ahn, Si-Young Choi
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Patent number: 7759192Abstract: A semiconductor device includes a capacitor having a bottom electrode, a dielectric layer formed on the bottom electrode, a top electrode formed on the dielectric layer, and a contact plug having a metal that is connected with the top electrode, wherein the top electrode includes a doped poly-Si1-xGex layer and a doped polysilicon layer epitaxially deposited on the doped poly-Si1-xGex layer and the contact plug makes a contact with the doped polysilicon layer.Type: GrantFiled: October 24, 2005Date of Patent: July 20, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Young Ahn, Jin-Tae Noh, Hee-Seok Kim, Jin-Gyun Kim, Ju-Wan Lim, Sang-Ryol Yang, Hong-Suk Kim, Sung-Hae Lee