Patents by Inventor Jintaek KANG
Jintaek KANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230342311Abstract: An accelerator, an operation method of the accelerator, and an accelerator system including the accelerator are disclosed. The operation method includes receiving one or more workloads assigned on an accelerator, determining reuse data of the workloads based on hardware resource information and/or a memory access cost of the accelerator when a plurality of processing units included in the accelerator performs the workloads, and providing a result of performing the workloads.Type: ApplicationFiled: June 22, 2023Publication date: October 26, 2023Applicants: SAMSUNG ELECTRONICS CO., LTD, SNU R&DB FOUNDATIONInventors: Seung Wook LEE, Soojung RYU, Jintaek KANG, Sunjung LEE
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Patent number: 11763153Abstract: A processor-implemented neural network method includes: generating a bit vector based on whether each of a plurality of input activations within a neural network is 0; merging the bit vector into the input activations such that bit values within the neural network included in the bit vector are most significant bits (MSBs) of multi bit expressions of the input activations; merging the bit vector into weights such that the bit values included in the bit vector are MSBs of multi bit expressions of the weights; sorting the input activations and the weights based on bits corresponding to the MSBs; and implementing the neural network, including performing operations between the sorted input activations and the sorted weights.Type: GrantFiled: October 12, 2022Date of Patent: September 19, 2023Assignees: Samsung Electronics Co., Ltd., Seoul National University R&DB FoundationInventors: Yoojin Kim, Soonhoi Ha, Donghyun Kang, Jintaek Kang
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Patent number: 11726929Abstract: An accelerator, an operation method of the accelerator, and an accelerator system including the accelerator are disclosed. The operation method includes receiving one or more workloads assigned by a host controller, determining reuse data of the workloads based on hardware resource information and/or a memory access cost of the accelerator when a plurality of processing units included in the accelerator performs the workloads, and providing a result of performing the workloads.Type: GrantFiled: February 2, 2021Date of Patent: August 15, 2023Assignees: Samsung Electronics Co., Ltd., SNU R&DB FOUNDATIONInventors: Seung Wook Lee, Soojung Ryu, Jintaek Kang, Sunjung Lee
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Publication number: 20230229931Abstract: A processor-implemented method of a neural network includes obtaining intermediate pooling results, respectively corresponding to sub-pooling kernels obtained by decomposing an original pooling kernel, by performing a pooling operation on input pixels included in a current window in an input feature map with the sub-pooling kernels, obtaining a final pooling result corresponding to the current window by post-processing the intermediate pooling results, and determining an output pixel value of an output feature map, based on the final pooling result, wherein the current window is determined according to the original pooling kernel having been slid, according to a raster scan order, in the input feature map.Type: ApplicationFiled: March 18, 2023Publication date: July 20, 2023Applicants: Samsung Electronics Co., Ltd., Seoul National University R&DB FoundationInventors: Hyunsun PARK, Soonhoi HA, Donghyun KANG, Jintaek KANG
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Patent number: 11640538Abstract: A processor-implemented method of a neural network includes obtaining intermediate pooling results, respectively corresponding to sub-pooling kernels obtained by decomposing an original pooling kernel, by performing a pooling operation on input pixels included in a current window in an input feature map with the sub-pooling kernels, obtaining a final pooling result corresponding to the current window by post-processing the intermediate pooling results, and determining an output pixel value of an output feature map, based on the final pooling result, wherein the current window is determined according to the original pooling kernel having been slid, according to a raster scan order, in the input feature map.Type: GrantFiled: March 23, 2020Date of Patent: May 2, 2023Assignees: Samsung Electronics Co., Ltd., Seoul National University R&DB FoundationInventors: Hyunsun Park, Soonhoi Ha, Donghyun Kang, Jintaek Kang
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Publication number: 20230031471Abstract: A processor-implemented neural network method includes: generating a bit vector based on whether each of a plurality of input activations within a neural network is 0; merging the bit vector into the input activations such that bit values within the neural network included in the bit vector are most significant bits (MSBs) of multi bit expressions of the input activations; merging the bit vector into weights such that the bit values included in the bit vector are MSBs of multi bit expressions of the weights; sorting the input activations and the weights based on bits corresponding to the MSBs; and implementing the neural network, including performing operations between the sorted input activations and the sorted weights.Type: ApplicationFiled: October 12, 2022Publication date: February 2, 2023Applicants: Samsung Electronics Co., Ltd., Seoul National University R&DB FoundationInventors: Yoojin KIM, Soonhoi HA, Donghyun KANG, Jintaek KANG
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Patent number: 11501166Abstract: A processor-implemented neural network method includes: generating a bit vector based on whether each of a plurality of input activations within a neural network is 0; merging the bit vector into the input activations such that bit values within the neural network included in the bit vector are most significant bits (MSBs) of multi bit expressions of the input activations; merging the bit vector into weights such that the bit values included in the bit vector are MSBs of multi bit expressions of the weights; sorting the input activations and the weights based on bits corresponding to the MSBs; and implementing the neural network, including performing operations between the sorted input activations and the sorted weights.Type: GrantFiled: April 24, 2020Date of Patent: November 15, 2022Assignees: Samsung Electronics Co., Ltd., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATIONInventors: Yoojin Kim, Soonhoi Ha, Donghyun Kang, Jintaek Kang
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Publication number: 20210263865Abstract: An accelerator, an operation method of the accelerator, and an accelerator system including the accelerator are disclosed. The operation method includes receiving one or more workloads assigned by a host controller, determining reuse data of the workloads based on hardware resource information and/or a memory access cost of the accelerator when a plurality of processing units included in the accelerator performs the workloads, and providing a result of performing the workloads.Type: ApplicationFiled: February 2, 2021Publication date: August 26, 2021Applicants: SAMSUNG ELECTRONICS CO., LTD, SNU R&DB FOUNDATIONInventors: Seung Wook LEE, Soojung RYU, Jintaek KANG, Sunjung LEE
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Publication number: 20210117781Abstract: A processor-implemented neural network method includes: generating a bit vector based on whether each of a plurality of input activations within a neural network is 0; merging the bit vector into the input activations such that bit values within the neural network included in the bit vector are most significant bits (MSBs) of multi bit expressions of the input activations; merging the bit vector into weights such that the bit values included in the bit vector are MSBs of multi bit expressions of the weights; sorting the input activations and the weights based on bits corresponding to the MSBs; and implementing the neural network, including performing operations between the sorted input activations and the sorted weights.Type: ApplicationFiled: April 24, 2020Publication date: April 22, 2021Applicants: Samsung Electronics Co., Ltd., Seoul National University R&DB FoundationInventors: Yoojin KIM, Soonhoi HA, Donghyun KANG, Jintaek KANG
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Publication number: 20210097403Abstract: A processor-implemented method of a neural network includes obtaining intermediate pooling results, respectively corresponding to sub-pooling kernels obtained by decomposing an original pooling kernel, by performing a pooling operation on input pixels included in a current window in an input feature map with the sub-pooling kernels, obtaining a final pooling result corresponding to the current window by post-processing the intermediate pooling results, and determining an output pixel value of an output feature map, based on the final pooling result, wherein the current window is determined according to the original pooling kernel having been slid, according to a raster scan order, in the input feature map.Type: ApplicationFiled: March 23, 2020Publication date: April 1, 2021Applicants: Samsung Electronics Co., Ltd., Seoul National University R&DB FoundationInventors: Hyunsun PARK, Soonhoi HA, Donghyun KANG, Jintaek KANG