Patents by Inventor Jinu J. Thomas
Jinu J. Thomas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10997012Abstract: A method for managing hardware within a computing system. The method includes at least one computer processors identifying a plurality of field-replaceable units (FRUs) within a computing system that respectively include a non-volatile memory device. The method further includes determining a status corresponding to a FRU of the identified plurality of FRUs. The method further includes responding to determining a non-functional status of the FRU of the identified plurality of FRUs, by determining a response related to the non-functional FRU. The method further includes initiating an action on the computing system based on the determined response related to the non-functional FRU.Type: GrantFiled: June 29, 2018Date of Patent: May 4, 2021Assignee: International Business machines CorporationInventors: Krishna Swaroop Athmaram, Santosh Puranik, Jinu J. Thomas
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Publication number: 20200004621Abstract: A method for managing hardware within a computing system. The method includes at least one computer processors identifying a plurality of field-replaceable units (FRUs) within a computing system that respectively include a non-volatile memory device. The method further includes determining a status corresponding to a FRU of the identified plurality of FRUs. The method further includes responding to determining a non-functional status of the FRU of the identified plurality of FRUs, by determining a response related to the non-functional FRU. The method further includes initiating an action on the computing system based on the determined response related to the non-functional FRU.Type: ApplicationFiled: June 29, 2018Publication date: January 2, 2020Inventors: Krishna Swaroop Athmaram, Santosh Puranik, Jinu J. Thomas
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Patent number: 10248446Abstract: A system plan for a single symmetric multiprocessing server having a plurality of computing nodes with a single hypervisor that spans across the plurality of computing nodes may be created based upon user defined parameters. Based upon the user defined parameters, an asymmetric cabling structure between the computing nodes of the single symmetric multiprocessing server for the system plan may be determined. In response to determining the asymmetric cabling structure, the system plan may be displayed to a user through a graphical user interface.Type: GrantFiled: September 30, 2015Date of Patent: April 2, 2019Assignee: International Business Machines CorporationInventors: Hariharasubramanian Ramasubramanian, Jinu J. Thomas, Venkatesh Sainath
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Patent number: 10243803Abstract: Disclosed aspects relate to service interface topology management for a shared pool of configurable computing resources. A management engine may detect a first linkage error event for a first set of data traffic with respect to a first service interface cable which connects a first global service processor with a set of hardware devices. A second service interface cable which connects a second global service processor with the set of hardware devices may be sensed. Based on and in response to the first linkage error event for the first set of data traffic, the management engine may determine to access the set of hardware devices by utilizing the second service interface cable. The first set of data traffic may be routed to the set of hardware devices via the second service interface cable.Type: GrantFiled: July 29, 2016Date of Patent: March 26, 2019Assignee: International Business Machines CorporationInventors: Gaurav Kakkar, Santosh S. Puranik, Jinu J. Thomas
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Patent number: 10171308Abstract: Disclosed aspects relate to dynamic cable-linkage management for a shared pool of configurable computing resources having a set of cable-linkage topology data. A first connection between a first service processor and a plurality of compute nodes may be sensed by a first mapping engine which is coupled with a first service processor on a set of control nodes. A plurality of node identifiers may be established on the plurality of compute nodes by the first mapping engine. Based on the plurality of node identifiers and the set of cable-linkage topology data, a first device path map may be determined. A set of data traffic may be routed via the first connection between the first service processor and the plurality of compute nodes based on the first device path map.Type: GrantFiled: August 20, 2016Date of Patent: January 1, 2019Assignee: International Business Machines CorporationInventors: Gaurav Kakkar, Santosh S. Puranik, Jinu J. Thomas
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Patent number: 10067842Abstract: Data communication between nodes of a symmetric multiprocessing (SMP) computing system can be maintained during the replacement of a faulty cable used to interconnect the nodes. A data bus error caused by the faulty cable is detected, resulting in the activation of an alternative data path between the nodes, and the disabling of a data path through the faulty cable. A system notification indicating the faulty cable is issued, and in response to the nodes being interconnected with a replacement cable, the replacement cable is tested for reliability. After the replacement cable is determined to be reliable, a data path through the replacement cable is activated.Type: GrantFiled: December 1, 2015Date of Patent: September 4, 2018Assignee: International Business Machines CorporationInventors: Santosh S. Puranik, Venkatesh Sainath, Jinu J. Thomas
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Patent number: 9940289Abstract: An approach is provided for preventing access to mis=plugged devices by a service processor (SP). The SP retrieves an expected device identifier of a device associated with a hot-plug event. The hot-plug event was received in response to the device being connected to a selected port of a service processor, and the port is one many ports included in the SP. The SP sends a request for a device identifier via the port and actual device identifier is received from the device. The device is validated by comparing the expected device identifier with the actual device identifier. If the identifiers match, a link between the SP and the device is maintained. On the other hand, if the identifiers do not match, the link between the SP and the device is terminated or otherwise inhibited.Type: GrantFiled: September 16, 2015Date of Patent: April 10, 2018Assignee: International Business Machines CorporationInventors: Douglas M. Boecker, Santosh S. Puranik, Jinu J. Thomas
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Publication number: 20180054362Abstract: Disclosed aspects relate to dynamic cable-linkage management for a shared pool of configurable computing resources having a set of cable-linkage topology data. A first connection between a first service processor and a plurality of compute nodes may be sensed by a first mapping engine which is coupled with a first service processor on a set of control nodes. A plurality of node identifiers may be established on the plurality of compute nodes by the first mapping engine. Based on the plurality of node identifiers and the set of cable-linkage topology data, a first device path map may be determined. A set of data traffic may be routed via the first connection between the first service processor and the plurality of compute nodes based on the first device path map.Type: ApplicationFiled: August 20, 2016Publication date: February 22, 2018Inventors: Gaurav Kakkar, Santosh S. Puranik, Jinu J. Thomas
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Publication number: 20180034704Abstract: Disclosed aspects relate to service interface topology management for a shared pool of configurable computing resources. A management engine may detect a first linkage error event for a first set of data traffic with respect to a first service interface cable which connects a first global service processor with a set of hardware devices. A second service interface cable which connects a second global service processor with the set of hardware devices may be sensed. Based on and in response to the first linkage error event for the first set of data traffic, the management engine may determine to access the set of hardware devices by utilizing the second service interface cable. The first set of data traffic may be routed to the set of hardware devices via the second service interface cable.Type: ApplicationFiled: July 29, 2016Publication date: February 1, 2018Inventors: Gaurav Kakkar, Santosh S. Puranik, Jinu J. Thomas
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Publication number: 20170153953Abstract: Data communication between nodes of a symmetric multiprocessing (SMP) computing system can be maintained during the replacement of a faulty cable used to interconnect the nodes. A data bus error caused by the faulty cable is detected, resulting in the activation of an alternative data path between the nodes, and the disabling of a data path through the faulty cable. A system notification indicating the faulty cable is issued, and in response to the nodes being interconnected with a replacement cable, the replacement cable is tested for reliability. After the replacement cable is determined to be reliable, a data path through the replacement cable is activated.Type: ApplicationFiled: December 1, 2015Publication date: June 1, 2017Inventors: Santosh S. Puranik, Venkatesh Sainath, Jinu J. Thomas
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Publication number: 20170090969Abstract: Data access patterns between at least three nodes within a single symmetric multiprocessing server may be monitored by at least one hypervisor. At the hypervisor, mappings for the data access patterns may be generated for the at least three nodes. Based upon the mappings, the hypervisor may determine that the data access patterns for at least two of the at least three nodes are outside of a bandwidth threshold. In response to determining that the data access patterns for at least two of the at least three nodes are outside of a bandwidth threshold, the hypervisor may formulate an asymmetric cabling plan. Based upon the asymmetric cabling plan, a recommendation to alter the multiprocessor fabric link aggregation may be displayed to a user through a graphical user interface.Type: ApplicationFiled: November 10, 2015Publication date: March 30, 2017Inventors: Hariharasubramanian Ramasubramanian, Jinu J. Thomas, Venkatesh Sainath
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Publication number: 20170090967Abstract: A system plan for a single symmetric multiprocessing server having a plurality of computing nodes with a single hypervisor that spans across the plurality of computing nodes may be created based upon user defined parameters. Based upon the user defined parameters, an asymmetric cabling structure between the computing nodes of the single symmetric multiprocessing server for the system plan may be determined. In response to determining the asymmetric cabling structure, the system plan may be displayed to a user through a graphical user interface.Type: ApplicationFiled: September 30, 2015Publication date: March 30, 2017Inventors: Hariharasubramanian Ramasubramanian, Jinu J. Thomas, Venkatesh Sainath
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Patent number: 9600322Abstract: Data access patterns between at least three nodes within a single symmetric multiprocessing server may be monitored by at least one hypervisor. At the hypervisor, mappings for the data access patterns may be generated for the at least three nodes. Based upon the mappings, the hypervisor may determine that the data access patterns for at least two of the at least three nodes are outside of a bandwidth threshold. In response to determining that the data access patterns for at least two of the at least three nodes are outside of a bandwidth threshold, the hypervisor may formulate an asymmetric cabling plan. Based upon the asymmetric cabling plan, a recommendation to alter the multiprocessor fabric link aggregation may be displayed to a user through a graphical user interface.Type: GrantFiled: November 10, 2015Date of Patent: March 21, 2017Assignee: International Business Machines CorporationInventors: Hariharasubramanian Ramasubramanian, Jinu J. Thomas, Venkatesh Sainath
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Publication number: 20170075850Abstract: An approach is provided for preventing access to mis=plugged devices by a service processor (SP). The SP retrieves an expected device identifier of a device associated with a hot-plug event. The hot-plug event was received in response to the device being connected to a selected port of a service processor, and the port is one many ports included in the SP. The SP sends a request for a device identifier via the port and actual device identifier is received from the device. The device is validated by comparing the expected device identifier with the actual device identifier. If the identifiers match, a link between the SP and the device is maintained. On the other hand, if the identifiers do not match, the link between the SP and the device is terminated or otherwise inhibited.Type: ApplicationFiled: September 16, 2015Publication date: March 16, 2017Inventors: Douglas M. Boecker, Santosh S. Puranik, Jinu J. Thomas
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Patent number: 9563464Abstract: Data access patterns between at least three nodes within a single symmetric multiprocessing server may be monitored by at least one hypervisor. At the hypervisor, mappings for the data access patterns may be generated for the at least three nodes. Based upon the mappings, the hypervisor may determine that the data access patterns for at least two of the at least three nodes are outside of a bandwidth threshold. In response to determining that the data access patterns for at least two of the at least three nodes are outside of a bandwidth threshold, the hypervisor may formulate an asymmetric cabling plan. Based upon the asymmetric cabling plan, a recommendation to alter the multiprocessor fabric link aggregation may be displayed to a user through a graphical user interface.Type: GrantFiled: September 30, 2015Date of Patent: February 7, 2017Assignee: International Business Machines CorporationInventors: Hariharasubramanian Ramasubramanian, Jinu J. Thomas, Venkatesh Sainath