Patents by Inventor Jin-Uk Shin
Jin-Uk Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11334109Abstract: A clock stretcher includes a delay line, a control unit, and a combiner. The delay line outputs a series of delayed phases of an input clock. The control circuit is clocked by the input clock. It outputs a series of delayed phase enable signals. The combiner circuit receives the delayed phases from the delay line and the delayed phase enable signals from the control circuit, and outputs a modified clock. The control circuit determines if stretching has started, if wraparound must occur, and if a next phase must be enabled. The combiner retimes a delayed phase enable signal for a first delayed phase using a flipflop clocked by a second delayed phase to generate a retimed phase enable signal. The combiner uses the retimed phase enable signal to pass a pulse of the first delayed phase to the output as a pulse of the modified clock.Type: GrantFiled: August 18, 2021Date of Patent: May 17, 2022Assignee: SambaNova Systems, Inc.Inventors: Fahim ur Rahman, Mahmood Khayatzadeh, Zuxu Qin, Jin-uk Shin
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Patent number: 11323124Abstract: A clock stretcher includes a DLL that derives delayed versions of an input clock signal, and a combiner that cyclically selects the delayed versions to generate a modified clock signal. The DLL has a phase error because of its finite bandwidth. The clock stretcher measures the phase error and corrects for a glitch in the modified clock signal by using the phase error when phase selection wraparound occurs. The clock stretcher may operate from a power supply that has droops, without intervening voltage regulation.Type: GrantFiled: June 3, 2021Date of Patent: May 3, 2022Assignee: SambaNova Systems, Inc.Inventors: Fahim ur Rahman, Mahmood Khayatzadeh, Zuxu Qin, Jin-Uk Shin
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Patent number: 11290113Abstract: A clock stretcher includes a digital DLL that derives delayed versions of an input clock signal, and a combiner that cyclically selects the delayed versions to generate a modified clock signal. The combiner uses a hop code, dependent on a sensed condition, to determine the step size for the cyclical selection. The digital DLL corrects its delay speed at discrete times, during which it may be active. If the DLL delay line becomes slower while it is active, the modified clock signal would incur a glitch. The clock stretcher corrects for this glitch by using an increased hop code when a speed change occurs. The clock stretcher may operate from a sensed power supply without intervening voltage regulation.Type: GrantFiled: June 3, 2021Date of Patent: March 29, 2022Assignee: SAMBANOVA SYSTEMS, INC.Inventors: Fahim ur Rahman, Sang-Min Lee, Jin-Uk Shin
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Patent number: 11290114Abstract: A clock stretcher includes a DLL that derives delayed versions of an input clock signal. The clock stretcher has passive and stretching modes. It operates from a sensed power supply without intervening voltage regulation. In passive mode, it forwards input clock pulses to the clock stretcher output. The input clock pulses are delayed by fewer than 10 DLL delay line delay stages. In stretching mode, a combiner cyclically selects the delayed versions of the input clock signal to generate a modified clock signal. The combiner uses a hop code, dependent on a sensed condition, to determine the step size for the cyclical selection. To enter passive mode, the clock stretcher tests if a passive mode entry threshold is met. The threshold includes two conditions: the hop code must be zero, and phase selection must have reached a wraparound point that may have been corrected for a delay line offset.Type: GrantFiled: June 3, 2021Date of Patent: March 29, 2022Assignee: SAMBANOVA SYSTEMS, INC.Inventors: Fahim ur Rahman, Mahmood Khayatzadeh, Jin-Uk Shin
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Patent number: 11239846Abstract: A clock stretcher includes a DLL that derives delayed versions of an input clock signal, and a combiner that cyclically selects the delayed versions to generate a modified clock signal. The combiner uses a hop code, dependent on a sensed condition, to determine the step size for the cyclical selection. The DLL may have a phase error that would cause a glitch in the modified clock during phase selection wraparound. The clock stretcher proactively increases the step size during wraparound by adding an offset skip parameter value to the hop code. The clock stretcher may operate from a sensed power supply without intervening voltage regulation.Type: GrantFiled: June 3, 2021Date of Patent: February 1, 2022Assignee: SambaNova Systems, Inc.Inventors: Fahim ur Rahman, Jin-Uk Shin
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Patent number: 10205375Abstract: An embodiment includes a circuit block configured to distribute a power signal to a plurality of voltage sense signals, and a voltage regulator configured to generate a regulated voltage level on the power signal. The embodiment also includes a sensing circuit configured to perform a sequence of comparisons of respective voltage levels of the plurality of voltage sense signals using a selection criterion. To perform the sequence of comparisons, the sensing circuit may be configured to select either a first voltage sense signal or a second voltage sense signal to generate a first output voltage sense signal. The sensing circuit may also be configured to select either a third voltage sense signal or a previously generated output voltage sense signal to generate a feedback signal. The voltage regulator circuit may be further configured to modify the regulated voltage level using the feedback signal.Type: GrantFiled: September 15, 2017Date of Patent: February 12, 2019Assignee: Oracle International CorporationInventors: Georgios Konstadinidis, Changku Hwang, Jin-Uk Shin
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Patent number: 9602086Abstract: A double half latch circuit includes a first stage coupled to receive a local input enable signal on an input of a second logic gate, and a complement of the clock signal on an input of a third logic gate, and further includes a fourth logic gate coupled to generate an intermediate enable signal based on states of the local input enable signal the complement of the clock signal. A second stage includes a fifth logic gate coupled to receive the complement of the clock signal, and a sixth logic gate coupled to receive the intermediate enable signal, and is configured to generate the output enable signal. The double half-latch circuit is transparent to the state changes of the local input enable signal when the clock signal is low and opaque to state changes of the local input enable signal when the clock signal is high.Type: GrantFiled: March 25, 2015Date of Patent: March 21, 2017Assignee: Oracle International CorporationInventors: He Huang, Mayur Joshi, Ha Pham, Jin-Uk Shin
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Publication number: 20160285440Abstract: A double half latch circuit includes a first stage coupled to receive a local input enable signal on an input of a second logic gate, and a complement of the clock signal on an input of a third logic gate, and further includes a fourth logic gate coupled to generate an intermediate enable signal based on states of the local input enable signal the complement of the clock signal. A second stage includes a fifth logic gate coupled to receive the complement of the clock signal, and a sixth logic gate coupled to receive the intermediate enable signal, and is configured to generate the output enable signal. The double half-latch circuit is transparent to the state changes of the local input enable signal when the clock signal is low and opaque to state changes of the local input enable signal when the clock signal is high.Type: ApplicationFiled: March 25, 2015Publication date: September 29, 2016Inventors: He Huang, Mayur Joshi, Ha Pham, Jin-Uk Shin
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Patent number: 9257972Abstract: A flip-flop circuit is disclosed. The flip-flop circuit includes pull-up and pull-down circuits each coupled to a data input and configured to be activated responsive to a clock signal transition from a first phase to a second phase, depending on the input data. A write circuit is configured to write data into a latch of the flip-flop responsive to activation of one of the pull-up and pull-down circuits. An output driver circuit includes a dynamic portion and a static portion, with the dynamic portion being activated responsive to activation of one of the pull-up and pull-down circuits. Activation of the dynamic portion may occur concurrently with writing of the data into the latch. The output driver circuit also includes a static portion. After the clock transitions back to the first phase, the static portion may drive and hold the output while the dynamic portion is deactivated.Type: GrantFiled: September 29, 2014Date of Patent: February 9, 2016Assignee: Oracle International CorporationInventors: Ha Pham, Jin-Uk Shin, Hiep Ngo
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Patent number: 8994429Abstract: Embodiments of a flip-flip circuit are disclosed that may allow a reduction in data setup time and lower switching power. The flip-flop circuit may include an input circuit, an output circuit, a clock circuit, and a feedback circuit. The clock circuit may be operable to generate internal clocks dependent upon received data, and the generated internal clocks may enable the feedback and input circuits.Type: GrantFiled: March 13, 2014Date of Patent: March 31, 2015Assignee: Oracle International CorporationInventors: Ha M Pham, Jin-uk Shin
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Patent number: 8860484Abstract: Embodiments of a logic path are disclosed that may allow for a reduction in switching power. The logic path may include a storage circuit, a comparison circuit, and a clock gating circuit. The storage circuit may be configured to store received data responsive to a local clock signal. The comparison circuit may be operable to compare the received data to data previously stored in the storage circuit. The clock gating circuit may be configured to generate the local clock signal dependent on a global clock signal, and de-activate the local clock signal dependent upon the results of the comparison performed by the comparison circuit.Type: GrantFiled: March 15, 2013Date of Patent: October 14, 2014Assignee: Oracle International CorporationInventors: Ha M Pham, Jin-uk Shin
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Publication number: 20140266334Abstract: Embodiments of a logic path are disclosed that may allow for a reduction in switching power. The logic path may include a storage circuit, a comparison circuit, and a clock gating circuit. The storage circuit may be configured to store received data responsive to a local clock signal. The comparison circuit may be operable to compare the received data to data previously stored in the storage circuit. The clock gating circuit may be configured to generate the local clock signal dependent on a global clock signal, and de-activate the local clock signal dependent upon the results of the comparison performed by the comparison circuit.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: ORACLE INTERNATIONAL CORPORATIONInventors: Ha M. Pham, Jin-uk Shin
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Publication number: 20140062083Abstract: The present invention relates to a method for reinforcing a connection tube having an expansion part, and to a connection tube having an expansion part reinforced by said method, characterized in that, in the method, a reinforcing tube manufactured using a homogeneous or heterogeneous synthetic resin, which is mounted on the outer surface of one end of a tube body formed by extruding a synthetic resin, and said tube body, in which the expansion part is to be formed, are heated to the glass transition temperature thereof. Then, the end of the tube body is fitted and fixed into an external former mold for expansion within a range in which said reinforcing tube is mounted, and an expansion member is inserted into the tube body so as to expand and form the end of the tube body on which the reinforcing tube is mounted.Type: ApplicationFiled: May 23, 2011Publication date: March 6, 2014Inventor: Jin-Uk Shin
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Publication number: 20140047886Abstract: A steam-blocking apparatus includes: a rolling mill configured to roll a material; a transfer roller disposed at a rear side of the rolling mill and configured to transfer the material from the rolling mill; a descaler disposed above the transfer roller and configured to spray wash water toward the transfer roller; a width-measuring part disposed at a rear side of the descaler and configured to measure the width of the material; and a shield disposed between the descaler and the width-measuring part and configured to prevent steam, generated from evaporation of the wash water, from being introduced into the width-measuring part.Type: ApplicationFiled: October 28, 2013Publication date: February 20, 2014Applicant: Hyundai Steel CompanyInventors: Yong Kook Park, Jong Hyob Lim, Hyeong Jin Kim, Ho Jin Nam, Jin Uk Shin, Kwan Hyung Lee, Hyun Jun Choi
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Patent number: 8446791Abstract: A process-tolerant large-swing sense amplifier with latching capability includes top-array and bottom-array access. The sense amplifier provides improved tolerance to process variation, reduces design complexity, reduces power consumption, and reduces the physical footprint of the circuit. In addition, the sense amplifier provides write-through functionality through the read data bus.Type: GrantFiled: December 3, 2010Date of Patent: May 21, 2013Assignee: Oracle International CorporationInventors: Ha M. Pham, Jin-Uk Shin, Vaibhav Gupta
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Patent number: 8324932Abstract: A static complementary transistor type logic gate circuit includes a plurality of input terminals for receiving a corresponding plurality of input signals, and an output terminal. The logic gate circuit further includes a first plurality of transistors of one conductivity type, arranged to form a plurality of pullup paths for selectively connecting the output terminal, through one or more intermediate nodes, to a positive supply voltage based on the plurality of input signals; and a second plurality of transistors of the complementary conductivity type, arranged to form a plurality of pulldown paths for selectively connecting the output terminal, through one or more intermediate nodes, to a negative supply voltage based on the plurality of input signals. A precharge device is configured to selectively charge an intermediate node to the far-side supply voltage when the intermediate node is disconnected from the near-side supply voltage and disconnected from the output terminal.Type: GrantFiled: November 23, 2010Date of Patent: December 4, 2012Assignee: Oracle International CorporationInventors: Jin-Uk Shin, Lancelot Y. Kwong, Gaurav Shrivastav
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Publication number: 20120140575Abstract: A process-tolerant large-swing sense amplifier with latching capability includes top-array and bottom-array access. The sense amplifier provides improved tolerance to process variation, reduces design complexity, reduces power consumption, and reduces the physical footprint of the circuit. In addition, the sense amplifier provides write-through functionality through the read data bus.Type: ApplicationFiled: December 3, 2010Publication date: June 7, 2012Applicant: ORACLE INTERNATIONAL CORPORATIONInventors: Ha M. Pham, Jin-Uk Shin, Vaibhav Gupta
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Publication number: 20120126852Abstract: A static complementary transistor type logic gate circuit includes a plurality of input terminals for receiving a corresponding plurality of input signals, and an output terminal. The logic gate circuit further includes a first plurality of transistors of one conductivity type, arranged to form a plurality of pullup paths for selectively connecting the output terminal, through one or more intermediate nodes, to a positive supply voltage based on the plurality of input signals; and a second plurality of transistors of the complementary conductivity type, arranged to form a plurality of pulldown paths for selectively connecting the output terminal, through one or more intermediate nodes, to a negative supply voltage based on the plurality of input signals. A precharge device is configured to selectively charge an intermediate node to the far-side supply voltage when the intermediate node is disconnected from the near-side supply voltage and disconnected from the output terminal.Type: ApplicationFiled: November 23, 2010Publication date: May 24, 2012Applicant: ORACLE INTERNATIONAL CORPORATIONInventors: Jin-Uk Shin, Lancelot Y. Kwong, Gaurav Shrivastav
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Patent number: 7752410Abstract: A hardware implemented method for accessing data in a multicycle operations cache is provided. In this hardware implemented method, a request to access the data in a sub-bank of the multicycle operations cache is received. If the sub-bank is accessed in a previous, consecutive clock cycle, then the request to access the data in the sub-bank is ignored. Else, if the sub-bank is not accessed in the previous, consecutive clock cycle, then the data is allowed to be accessed in the sub-bank. A memory chip and a system for accessing data in the multicycle operations cache also are described.Type: GrantFiled: January 14, 2005Date of Patent: July 6, 2010Assignee: Oracle America, Inc.Inventors: Jin-Uk Shin, Effendy Kumala
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Patent number: 7084671Abstract: A Negative Bias Temperature Instability (NBTI) tolerant sense amplifier is provided. The sense amplifier includes an input stage having a pair of balanced isolation devices. Each of the balanced isolation devices has an input connected to receive a separate one of a pair of differential input signals. Each of the balanced isolation devices also has a gate that is connected to receive a common bias voltage. The sense amplifier further includes a sense stage connected to the input stage. The sense stage is configured to receive and amplify a higher signal to be provided by the pair of balanced isolation devices. The sense amplifier is also equipped to operate a low voltage levels.Type: GrantFiled: January 26, 2004Date of Patent: August 1, 2006Assignee: Sun Microsystems, Inc.Inventors: Dennis Wendell, Howard L. Levy, Jin-Uk Shin