Patents by Inventor Jin-won Jeong

Jin-won Jeong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240128123
    Abstract: A method for forming a semiconductor die, includes forming an interlayer dielectric layer on a substrate having a semiconductor die region, a seal-ring region, and a scribe line region, forming a metal pad and a test pad on the interlayer dielectric layer, forming a passivation dielectric layer on the interlayer dielectric layer, the metal pad, and the test pad, first etching the passivation dielectric layer and the interlayer dielectric layer existing between the seal-ring region and the scribe line region to a predetermined depth using a plasma etching process, second etching the passivation dielectric layer to expose the metal pad and the test pad, forming a bump on the metal pad, and dicing the substrate while removing the scribe line region by mechanical sawing.
    Type: Application
    Filed: December 18, 2023
    Publication date: April 18, 2024
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventors: Jin Won JEONG, Jang Hee LEE, Young Hun JUN, Jong Woon LEE, Jae Sik CHOI
  • Patent number: 11937472
    Abstract: An manufacturing method of a display device may include the following steps: forming a transistor on a substrate; forming an insulating layer on the transistor; forming a conductive layer including silver on the insulating layer; forming a photosensitive member on the conductive layer; forming an electrode of a light-emitting element by etching the conductive layer; performing plasma treatment on a structure that comprises the electrode, the plasma treatment using a gas including a halogen; and removing a product that is resulted from the plasma treatment.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: March 19, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sang Gab Kim, Hyun Min Cho, Tae Sung Kim, Yu-Gwang Jeong, Su Bin Bae, Jin Seock Kim, Sang Gyun Kim, Hyo Min Ko, Kil Won Cho, Hansol Lee
  • Publication number: 20240088469
    Abstract: A battery module includes a sub module including a cell stack having a plurality of battery cells and a pair of bus bar frames respectively coupled to one side and the other side of the cell stack; a module housing configured to accommodate the sub module and configured to have an air inlet and an air outlet formed to circulate air; a sprinkler provided through the module housing at one side of the cell stack in a stacking direction; and an outlet closing device configured to move by a buoyancy generated by a cooling water introduced into the module housing through the sprinkler so that the air outlet is closed.
    Type: Application
    Filed: March 4, 2021
    Publication date: March 14, 2024
    Applicant: LG ENERGY SOLUTION, LTD.
    Inventors: Seung-Hyun KIM, Ji-Won JEONG, Kyung-Hyun BAE, Jin-Kyu SHIN, Jin-Kyu LEE
  • Patent number: 11901322
    Abstract: A semiconductor chip packaging method includes forming a bump on a wafer, forming a coating film covering the bump, laser grooving the wafer, plasma etching the wafer on which the laser grooving is performed, exposing the bump by removing the coating film covering the bump, fabricating a semiconductor die by performing mechanical sawing of the wafer, and packaging the semiconductor die.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: February 13, 2024
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Jin Won Jeong, Jae Sik Choi, Byeung Soo Song
  • Patent number: 11887892
    Abstract: A method for forming a semiconductor die, includes forming an interlayer dielectric layer on a substrate having a semiconductor die region, a seal-ring region, and a scribe line region, forming a metal pad and a test pad on the interlayer dielectric layer, forming a passivation dielectric layer on the interlayer dielectric layer, the metal pad, and the test pad, first etching the passivation dielectric layer and the interlayer dielectric layer existing between the seal-ring region and the scribe line region to a predetermined depth using a plasma etching process, second etching the passivation dielectric layer to expose the metal pad and the test pad, forming a bump on the metal pad, and dicing the substrate while removing the scribe line region by mechanical sawing.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: January 30, 2024
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Jin Won Jeong, Jang Hee Lee, Young Hun Jun, Jong Woon Lee, Jae Sik Choi
  • Patent number: 11605052
    Abstract: The present disclosure provides systems and methods for monitoring inventory transfer in real-time, comprising a memory storing instructions and a processor configured to execute the instructions to receive a tote identifier associated with a tote configured to store one or more products and receive a container identifier associated with a container configured to store the tote. The processor is configured to receive, from a user device in the first fulfillment center, a code associated with a vehicle for transferring the container from a first to a second fulfillment center, receive, from a user device in the second fulfillment center, the code associated with the vehicle, receive, from the user device in the second fulfillment center, at least one of the container identifier or the tote identifier, and validate the transfer of the first product, based on the code and at least one of the container identifier or the tote identifier.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: March 14, 2023
    Assignee: Coupang Corp.
    Inventors: Ji Won Hwang, Seon Sook Hong, Jong Won Lee, Jin Won Jeong, Sang Min Jeon
  • Publication number: 20220278064
    Abstract: A semiconductor chip packaging method includes forming a bump on a wafer, forming a coating film covering the bump, laser grooving the wafer, plasma etching the wafer on which the laser grooving is performed, exposing the bump by removing the coating film covering the bump, fabricating a semiconductor die by performing mechanical sawing of the wafer, and packaging the semiconductor die.
    Type: Application
    Filed: May 18, 2022
    Publication date: September 1, 2022
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventors: Jin Won JEONG, Jae Sik CHOI, Byeung Soo SONG
  • Patent number: 11380640
    Abstract: A semiconductor chip packaging method includes forming a bump on a wafer, forming a coating film covering the bump, laser grooving the wafer, plasma etching the wafer on which the laser grooving is performed, exposing the bump by removing the coating film covering the bump, fabricating a semiconductor die by performing mechanical sawing of the wafer, and packaging the semiconductor die.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: July 5, 2022
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Jin Won Jeong, Jae Sik Choi, Byeung Soo Song
  • Patent number: 11238405
    Abstract: Provided is a method of recognizing an item as a removal target based on expiration date-related information of the item, acquiring information regarding an actual quantity of the removal target and a remaining quantity among the actual quantity, and updating information regarding stock based on the acquired information, and an electronic apparatus therefor.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: February 1, 2022
    Assignee: Coupang Corp.
    Inventors: Da Young Kim, Sang Min Jun, Jin Won Jeong, Kyeong Suk Jin, Woo Jung Park
  • Patent number: 11233000
    Abstract: A semiconductor package includes a first metal interconnection disposed in a semiconductor chip, a first bump group configured to be connected to the first metal interconnection, a first inner lead pattern group configured to be connected to the first bump group, a second metal interconnection disposed in the semiconductor chip, a second bump group configured to be connected to the second metal interconnection; and a second inner lead pattern group configured to be connected to the second bump group, wherein a density of the first metal interconnection is greater than a density of the second metal interconnection, such that a first pitch of the first lead pattern group is greater than a second pitch of the second lead pattern group.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: January 25, 2022
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Jae Sik Choi, Do Young Kim, Jin Won Jeong, Hye Ji Lee
  • Publication number: 20220005733
    Abstract: A method for forming a semiconductor die, includes forming an interlayer dielectric layer on a substrate having a semiconductor die region, a seal-ring region, and a scribe line region, forming a metal pad and a test pad on the interlayer dielectric layer, forming a passivation dielectric layer on the interlayer dielectric layer, the metal pad, and the test pad, first etching the passivation dielectric layer and the interlayer dielectric layer existing between the seal-ring region and the scribe line region to a predetermined depth using a plasma etching process, second etching the passivation dielectric layer to expose the metal pad and the test pad, forming a bump on the metal pad, and dicing the substrate while removing the scribe line region by mechanical sawing.
    Type: Application
    Filed: April 15, 2021
    Publication date: January 6, 2022
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventors: Jin Won JEONG, Jang Hee LEE, Young Hun JUN, Jong Woon LEE, Jae Sik CHOI
  • Publication number: 20210407854
    Abstract: A semiconductor die forming method includes preparing a wafer, forming a low-k dielectric layer on the wafer, forming a metal pad on the low-k dielectric layer, forming a passivation layer on the metal pad, patterning the passivation layer, laser grooving the low-k dielectric layer using an ultrashort pulse laser, and cutting the wafer by mechanical sawing to form one or more semiconductor dies.
    Type: Application
    Filed: April 15, 2021
    Publication date: December 30, 2021
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventors: Jin Won JEONG, Jae Sik CHOI, Byeung Soo SONG
  • Publication number: 20210350317
    Abstract: The present disclosure provides systems and methods for monitoring inventory transfer in real-time, comprising a memory storing instructions and a processor configured to execute the instructions to receive a tote identifier associated with a tote configured to store one or more products and receive a container identifier associated with a container configured to store the tote. The processor is configured to receive, from a user device in the first fulfillment center, a code associated with a vehicle for transferring the container from a first to a second fulfillment center, receive, from a user device in the second fulfillment center, the code associated with the vehicle, receive, from the user device in the second fulfillment center, at least one of the container identifier or the tote identifier, and validate the transfer of the first product, based on the code and at least one of the container identifier or the tote identifier.
    Type: Application
    Filed: July 23, 2021
    Publication date: November 11, 2021
    Applicant: Coupang Corp.
    Inventors: Ji Won HWANG, Seon Sook HONG, Jong Won LEE, Jin Won JEONG, Sang Min JEON
  • Publication number: 20210296271
    Abstract: A semiconductor chip packaging method includes forming a bump on a wafer, forming a coating film covering the bump, laser grooving the wafer, plasma etching the wafer on which the laser grooving is performed, exposing the bump by removing the coating film covering the bump, fabricating a semiconductor die by performing mechanical sawing of the wafer, and packaging the semiconductor die.
    Type: Application
    Filed: July 21, 2020
    Publication date: September 23, 2021
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventors: Jin Won JEONG, Jae Sik CHOI, Byeung Soo SONG
  • Patent number: 11107033
    Abstract: The present disclosure provides systems and methods for monitoring inventory transfer in real-time, comprising a memory storing instructions and a processor configured to execute the instructions to receive a tote identifier associated with a tote configured to store one or more products and receive a container identifier associated with a container configured to store the tote. The processor is configured to receive, from a user device in the first fulfillment center, a code associated with a vehicle for transferring the container from a first to a second fulfillment center, receive, from a user device in the second fulfillment center, the code associated with the vehicle, receive, from the user device in the second fulfillment center, at least one of the container identifier or the tote identifier, and validate the transfer of the first product, based on the code and at least one of the container identifier or the tote identifier.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: August 31, 2021
    Assignee: Coupang Corp.
    Inventors: Ji Won Hwang, Seon Sook Hong, Jong Won Lee, Jin Won Jeong, Sang Min Jeon
  • Patent number: 11097240
    Abstract: The present invention relates to a pickering emulsion composition using polyimide particles and a method for preparing the same. The pickering emulsion stabilized by the polyimide particles according to the present invention has a very stable dispersed phase and does not cause flocculation, creaming, coalescence and phase separation even after a long time, and has an advantage of being capable of forming both an oil-in-water type emulsion and a water-in-oil type emulsion. Further, the polyimide particles used in the present invention can be synthesized in a simple manner and have partial wettability without the surface treatment and pH control so that they can be easily used for the emulsion stabilization.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: August 24, 2021
    Assignees: UNIVERSITY INDUSTRY FOUNDATION, YONSEI UNIVERSITY WONJU CAMPUS, RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Chan Moon Chung, Kwang Myong Lee, Yu Jin Cho, Ju Young Choi, Beom Jun Kim, Jin Won Jeong, Dong Min Kim
  • Publication number: 20210256460
    Abstract: Provided is a method of recognizing an item as a removal target based on expiration date-related information of the item, acquiring information regarding an actual quantity of the removal target and a remaining quantity among the actual quantity, and updating information regarding stock based on the acquired information, and an electronic apparatus therefor.
    Type: Application
    Filed: September 16, 2020
    Publication date: August 19, 2021
    Inventors: Da Young Kim, Sang Min Jun, Jin Won Jeong, Kyeong Suk Jin, Woo Jung Park
  • Publication number: 20210065100
    Abstract: The present disclosure provides systems and methods for monitoring inventory transfer in real-time, comprising a memory storing instructions and a processor configured to execute the instructions to receive a tote identifier associated with a tote configured to store one or more products and receive a container identifier associated with a container configured to store the tote. The processor is configured to receive, from a user device in the first fulfillment center, a code associated with a vehicle for transferring the container from a first to a second fulfillment center, receive, from a user device in the second fulfillment center, the code associated with the vehicle, receive, from the user device in the second fulfillment center, at least one of the container identifier or the tote identifier, and validate the transfer of the first product, based on the code and at least one of the container identifier or the tote identifier.
    Type: Application
    Filed: August 26, 2019
    Publication date: March 4, 2021
    Applicant: Coupang, Corp.
    Inventors: Ji Won HWANG, Seon Sook HONG, Jong Won LEE, Jin Won JEONG, Sang Min JEON
  • Patent number: 10910270
    Abstract: A manufacturing and packaging method for a semiconductor die is provided. The method prepares a wafer which has a seal-ring region, forms a first interlayer insulating film on the wafer, forms a metal wiring in the first interlayer insulating film, forms a second interlayer insulating film on the first interlayer insulating film, forms metal pads on the second interlayer insulating film, forms a passivation layer on the metal pads, removes a portion of the passivation layer in a region adjacent to the seal-ring region to expose the second interlayer insulating film, etches a portion of the second interlayer insulating film, forms a bump on the metal pads, removes the first interlayer insulating film and the second interlayer insulating film in the region adjacent to the seal-ring region by a laser grooving process, and dices the wafer into a first semiconductor die and a second semiconductor die.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: February 2, 2021
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Jae Sik Choi, Jin Won Jeong, Byeung Soo Song, Dong Ki Shim, Jin Han Bae
  • Publication number: 20200312715
    Abstract: A manufacturing and packaging method for a semiconductor die is provided. The method prepares a wafer which has a seal-ring region, forms a first interlayer insulating film on the wafer, forms a metal wiring in the first interlayer insulating film, forms a second interlayer insulating film on the first interlayer insulating film, forms metal pads on the second interlayer insulating film, forms a passivation layer on the metal pads, removes a portion of the passivation layer in a region adjacent to the seal-ring region to expose the second interlayer insulating film, etches a portion of the second interlayer insulating film, forms a bump on the metal pads, removes the first interlayer insulating film and the second interlayer insulating film in the region adjacent to the seal-ring region by a laser grooving process, and dices the wafer into a first semiconductor die and a second semiconductor die.
    Type: Application
    Filed: July 30, 2019
    Publication date: October 1, 2020
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventors: Jae Sik CHOI, Jin Won JEONG, Byeung Soo SONG, Dong Ki SHIM, Jin Han BAE