Patents by Inventor Jinxia Bai
Jinxia Bai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Neural processing unit (NPU) direct memory access (NDMA) hardware pre-processing and post-processing
Patent number: 11861484Abstract: A neural processing unit (NPU) is described. The NPU includes an NPU direct memory access (NDMA) core. The NDMA core includes a read engine having a read buffer. The NDMA core also includes a write engine having a write buffer. The NPU also includes a controller. The controller is configured to direct the NDMA core to perform hardware pre-processing of NDMA data in the read buffer and post-processing of NDMA data in the write buffer on blocks of a data stripe to process tensors in artificial neural networks.Type: GrantFiled: September 28, 2018Date of Patent: January 2, 2024Assignee: QUALCOMM IncorporatedInventors: Jinxia Bai, Rosario Cammarota, Michael Goldfarb -
Patent number: 11763141Abstract: A neural processing unit (NPU) is described. The NPU includes an NPU direct memory access (NDMA) core. The NDMA core includes a read engine having a read buffer. The NDMA core also includes a write engine having a write buffer. The NPU also includes a controller. The controller is configured to direct the NDMA core to perform hardware memory bandwidth optimization for reading/writing NDMA data in the read buffer and/or NDMA data in the write buffer. The NDMA core is also configured to transparently combine NDMA transaction requests for a data stripe to increase local access to available tensors in artificial neural networks.Type: GrantFiled: April 4, 2022Date of Patent: September 19, 2023Assignee: QUALCOMM IncorporatedInventors: Jinxia Bai, Rosario Cammarota, Michael Goldfarb
-
Publication number: 20220230058Abstract: A neural processing unit (NPU) is described. The NPU includes an NPU direct memory access (NDMA) core. The NDMA core includes a read engine having a read buffer. The NDMA core also includes a write engine having a write buffer. The NPU also includes a controller. The controller is configured to direct the NDMA core to perform hardware memory bandwidth optimization for reading/writing NDMA data in the read buffer and/or NDMA data in the write buffer. The NDMA core is also configured to transparently combine NDMA transaction requests for a data stripe to increase local access to available tensors in artificial neural networks.Type: ApplicationFiled: April 4, 2022Publication date: July 21, 2022Inventors: Jinxia BAI, Rosario CAMMAROTA, Michael GOLDFARB
-
Patent number: 11295205Abstract: A neural processing unit (NPU) is described. The NPU includes an NPU direct memory access (NDMA) core. The NDMA core includes a read engine having a read buffer. The NDMA core also includes a write engine having a write buffer. The NPU also includes a controller. The controller is configured to direct the NDMA core to perform hardware memory bandwidth optimization for reading/writing NDMA data in the read buffer and/or NDMA data in the write buffer. The NDMA core is also configured to transparently combine NDMA transaction requests for a data stripe to increase local access to available tensors in artificial neural networks.Type: GrantFiled: September 28, 2018Date of Patent: April 5, 2022Assignee: Qualcomm IncorporatedInventors: Jinxia Bai, Rosario Cammarota, Michael Goldfarb
-
NEURAL PROCESSING UNIT (NPU) DIRECT MEMORY ACCESS (NDMA) HARDWARE PRE-PROCESSING AND POST-PROCESSING
Publication number: 20200104690Abstract: A neural processing unit (NPU) is described. The NPU includes an NPU direct memory access (NDMA) core. The NDMA core includes a read engine having a read buffer. The NDMA core also includes a write engine having a write buffer. The NPU also includes a controller. The controller is configured to direct the NDMA core to perform hardware pre-processing of NDMA data in the read buffer and post-processing of NDMA data in the write buffer on blocks of a data stripe to process tensors in artificial neural networks.Type: ApplicationFiled: September 28, 2018Publication date: April 2, 2020Inventors: Jinxia BAI, Rosario CAMMAROTA, Michael GOLDFARB -
Publication number: 20200104076Abstract: The present disclosure provides a method of accessing data from a first memory. The method may include receiving a command for accessing a first portion of the data. The data includes a plurality of words arranged as a multi-dimensional array of words that is stored contiguously in the first memory. The method may further include mapping the first portion of the data to a first portion of the plurality of words. The first portion of the plurality of words is not stored contiguously in the first memory. The method may further include accessing the first portion of the plurality of words while refraining from accessing at least a second portion of the plurality of words that is contiguously stored between at least two words of the first portion of the plurality of words.Type: ApplicationFiled: September 27, 2019Publication date: April 2, 2020Inventors: Jinxia BAI, Rosario CAMMAROTA, Michael GOLDFARB
-
Publication number: 20200104691Abstract: A neural processing unit (NPU) is described. The NPU includes an NPU direct memory access (NDMA) core. The NDMA core includes a read engine having a read buffer. The NDMA core also includes a write engine having a write buffer. The NPU also includes a controller. The controller is configured to direct the NDMA core to perform hardware memory bandwidth optimization for reading/writing NDMA data in the read buffer and/or NDMA data in the write buffer. The NDMA core is also configured to transparently combine NDMA transaction requests for a data stripe to increase local access to available tensors in artificial neural networks.Type: ApplicationFiled: September 28, 2018Publication date: April 2, 2020Inventors: Jinxia BAI, Rosario CAMMAROTA, Michael GOLDFARB
-
Patent number: 10120581Abstract: Aspects for generating compressed data streams with lookback pre-fetch instructions are disclosed. A data compression system is provided and configured to receive and compress an uncompressed data stream as part of a lookback-based compression scheme. The data compression system determines if a current data block was previously compressed. If so, the data compression system is configured to insert a lookback instruction corresponding to the current data block into the compressed data stream. Each lookback instruction includes a lookback buffer index that points to an entry in a lookback buffer where decompressed data corresponding to the data block will be stored during a separate decompression scheme. Once the data blocks have been compressed, the data compression system is configured to move a lookback buffer index of each lookback instruction in the compressed data stream into a lookback pre-fetch instruction located earlier than the corresponding lookback instruction in the compressed data stream.Type: GrantFiled: March 30, 2016Date of Patent: November 6, 2018Assignee: QUALCOMM IncorporatedInventors: Richard Senior, Amin Ansari, Vito Remo Bica, Jinxia Bai
-
Patent number: 9998143Abstract: A system for data decompression may include a processor coupled to a remote memory having a remote dictionary stored thereon and coupled to a decompression logic having a local memory with a local dictionary. The processor may decompress data during execution by accessing the local dictionary, and if necessary, the remote dictionary.Type: GrantFiled: August 5, 2016Date of Patent: June 12, 2018Assignee: QUALCOMM IncorporatedInventors: Richard Senior, Amin Ansari, Jinxia Bai, Vito Bica
-
Publication number: 20170285939Abstract: Aspects for generating compressed data streams with lookback pre-fetch instructions are disclosed. A data compression system is provided and configured to receive and compress an uncompressed data stream as part of a lookback-based compression scheme. The data compression system determines if a current data block was previously compressed. If so, the data compression system is configured to insert a lookback instruction corresponding to the current data block into the compressed data stream. Each lookback instruction includes a lookback buffer index that points to an entry in a lookback buffer where decompressed data corresponding to the data block will be stored during a separate decompression scheme. Once the data blocks have been compressed, the data compression system is configured to move a lookback buffer index of each lookback instruction in the compressed data stream into a lookback pre-fetch instruction located earlier than the corresponding lookback instruction in the compressed data stream.Type: ApplicationFiled: March 30, 2016Publication date: October 5, 2017Inventors: Richard Senior, Amin Ansari, Vito Remo Bica, Jinxia Bai
-
Publication number: 20160344406Abstract: A system for data decompression may include a processor coupled to a remote memory having a remote dictionary stored thereon and coupled to a decompression logic having a local memory with a local dictionary. The processor may decompress data during execution by accessing the local dictionary, and if necessary, the remote dictionary.Type: ApplicationFiled: August 5, 2016Publication date: November 24, 2016Inventors: Richard SENIOR, Amin ANSARI, Jinxia BAI, Vito BICA
-
Publication number: 20160248441Abstract: A system for data decompression may include a processor coupled to a remote memory having a remote dictionary stored thereon and coupled to a decompression logic having a local memory with a local dictionary. The processor may decompress data during execution by accessing the local dictionary, and if necessary, the remote dictionary.Type: ApplicationFiled: February 19, 2015Publication date: August 25, 2016Inventors: Richard SENIOR, Amin ANSARI, Jinxia BAI, Vito BICA
-
Patent number: 9413386Abstract: A system for data decompression may include a processor coupled to a remote memory having a remote dictionary stored thereon and coupled to a decompression logic having a local memory with a local dictionary. The processor may decompress data during execution by accessing the local dictionary, and if necessary, the remote dictionary.Type: GrantFiled: February 19, 2015Date of Patent: August 9, 2016Assignee: QUALCOMM IncorporatedInventors: Richard Senior, Amin Ansari, Jinxia Bai, Vito Bica
-
Patent number: 8612504Abstract: Techniques for performing IFFT pipelining are described. In some aspects, the pipelining is achieved with a processing system having a memory having first and second sections, an encoder configured to process data in each of the first and second memory sections, an IFFT configured to process the encoded data in the first and second memory sections, and a post-processor configured to process the IFFT processed data in the first memory section while the IFFT is processing the encoded data in the second memory section, the post processor configured to operate at a different clock speed than the encoder or the IFFT.Type: GrantFiled: December 18, 2006Date of Patent: December 17, 2013Assignee: QUALCOMM IncorporatedInventors: Jai N. Subrahmanyam, Chinnappa K. Ganapathy, Durk L. Van Veen, Jinxia Bai, Kevin S. Cousineau, Seokyong Oh
-
Patent number: 8543629Abstract: Techniques for perforating IFFT pipelining are described. In some aspects, the pipelining is achieved with a processing system having a memory with a first, second and third sections, an encoder configured to process data in each of the first, second and third memory sections in a round robin fashion, an IFFT configured to process the encoded data in each of the first, second, and third sections in a round robin fashion, and a post-processor configured to process the IFFT processed data in each of the first, second and third memory sections in a round robin fashion.Type: GrantFiled: December 18, 2006Date of Patent: September 24, 2013Assignee: QUALCOMM IncorporatedInventors: Jai N. Subrahmanyam, Chinnappa K. Ganapathy, Durk L. Van Veen, Jinxia Bai, Kevin S. Cousineau, Seokyong Oh
-
Patent number: 8213548Abstract: Methods and apparatus for dynamic packet reordering. In an aspect, a method is provided for processing slot data on-the-fly to produce decodable packets, wherein the slot data includes interleaved modulation symbols. The method includes de-interleaving a stream of the interleaved modulation symbols to produce a stream of modulation symbols, calculating parallel streams of LLR metrics based on the stream of modulation symbols, and mapping the parallel streams of LLR metrics to produce a stream of decodable packets. In another aspect, an apparatus is provided the includes de-interleaving logic to de-interleave a stream of interleaved modulation symbols to produce a stream of modulation symbols, metric processing logic configured to produce parallel streams of LLR metrics based on the stream of modulation symbols, and mapping logic configured to map the parallel streams of LLR metrics to produce a stream of decodable packets.Type: GrantFiled: April 4, 2006Date of Patent: July 3, 2012Assignee: Qualcomm IncorporatedInventors: Jinxia Bai, Chinnappa K. Ganapathy, Thomas Sun
-
Patent number: 8139612Abstract: Methods and apparatus for dynamic packet mapping. A method is provided for mapping metric data to produce a decodable packet associated with a channel. The method includes obtaining a channel identifier associated with metric data, determining an available buffer from a plurality of buffers based on the channel identifier, writing the metric data to the available buffer, detecting when a decodable packet is formed in a selected buffer of the plurality of buffers, and outputting the decodable packet from the selected buffer. An apparatus includes a plurality of buffers and mapping logic that is configured to obtain a channel identifier associated with metric data, determine an available buffer based on the channel identifier, write the metric data to the available buffer, detect when a decodable packet is formed in a selected buffer, and output the decodable packet from the selected buffer.Type: GrantFiled: April 4, 2006Date of Patent: March 20, 2012Assignee: QUALCOMM IncorporatedInventors: Jinxia Bai, Chinnappa K. Ganapathy, Thomas Sun
-
Patent number: 8102949Abstract: A system and method are provided for generating bit log likelihood ratio (LLR) values for two-layered Quadrature Phase-Shift Keying (QPSK) turbo decoding in a wireless communications user terminal (UT). The method includes receiving a two-layered QPSK signal with an energy ratio that is unknown, but typically defined as either k12 or k22. The method selects a mismatched energy ratio (k2) between k12 and k22, and generating bit LLR values for two-layered QPSK turbo decoding, using the mismatched k2 energy ratio. For example, if the received two-layered QPSK signal is known to have an energy ratio of about 4 or about 6.25. Then, k2 is selected to be about 5.0625. Alternately stated, the mismatched k2 energy ratio in selected by determining the approximate midpoint between k12 and k22.Type: GrantFiled: December 23, 2009Date of Patent: January 24, 2012Assignee: QUALCOMM IncorporatedInventors: Fuyun Ling, Seong Taek Chung, Jinxia Bai, Thomas Sun
-
Publication number: 20110032015Abstract: A method, apparatus and system for correcting different clock domains are disclosed. The disclosed implementations correct a second clock domain by making reference to a resampling filter, or similar device, used to correct a first clock domain. The implementations thereby facilitate clock correction using fewer or a different variety of elements.Type: ApplicationFiled: June 3, 2010Publication date: February 10, 2011Applicant: QUALCOMM IncorporatedInventors: Jinxia Bai, Linbo Li
-
Patent number: 7830957Abstract: Systems and methods are provided to process wireless data packets. A method includes determining a subset of data bits to be processed at a wireless transmitter and employing a clock edge to store the data. The clock edge allows parallel mapping of at least two bits from the subset of data bits into an interleaver memory per a given clock edge. From the memory, other encoding and scrambling processes are applied before transmitting the data packets across a wireless network.Type: GrantFiled: May 2, 2006Date of Patent: November 9, 2010Assignee: QUALCOMM IncorporatedInventors: Jinxia Bai, Thomas Sun