Abstract: A semiconductor apparatus includes a bus inversion information (DBI) processing unit configured to, when receiving multi-bit data, calculating DBI information of the data, and outputting a plurality of DBI flag signals, generate the plurality of DBI flag signals such that each DBI flag signal reflects DBI information of predetermined bits of the data, a first CRC processing unit configured to calculate cyclic redundancy check (CRC) information using the multi-bit data and partial DBI flag signals calculated among the plurality of DBI flag signals and output a plurality of CRC signals, and a second CRC processing unit configured to output CRC codes using the plurality of CRC signals and remaining DBI flag signals calculated among the plurality of the DBI flag signals.

Abstract: A semiconductor apparatus includes a bus inversion information (DBI) processing unit configured to, when receiving multi-bit data, calculating DBI information of the data, and outputting a plurality of DBI flag signals, generate the plurality of DBI flag signals such that each DBI flag signal reflects DBI information of predetermined bits of the data, a first CRC processing unit configured to calculate cyclic redundancy check (CRC) information using the multi-bit data and partial DBI flag signals calculated among the plurality of DBI flag signals and output a plurality of CRC signals, and a second CRC processing unit configured to output CRC codes using the plurality of CRC signals and remaining DBI flag signals calculated among the plurality of the DBI flag signals.

Abstract: A sense amplifier resistant to malfunctions associated with offsets in inverter pairs is presented. The sense amplifier includes inverter pairs and a controller. Any one input terminal of the inverter pairs is electrically connected to a bit line and the other one input terminal is electrically connected to a /bit line. The controller is configured to precharge the bit line and the /bit line to a level corresponding to an offset of the inverter pairs in response to a first control signal. The controller senses a voltage difference of the bit line and the /bit line using the inverter pairs by connecting output terminals of the inverter pairs to the bit line pairs in response to a second control signal.

Abstract: A sense amplifier resistant to malfunctions associated with offsets in inverter pairs is presented. The sense amplifier includes inverter pairs and a controller. Any one input terminal of the inverter pairs is electrically connected to a bit line and the other one input terminal is electrically connected to a /bit line. The controller is configured to precharge the bit line and the /bit line to a level corresponding to an offset of the inverter pairs in response to a first control signal. The controller senses a voltage difference of the bit line and the /bit line using the inverter pairs by connecting output terminals of the inverter pairs to the bit line pairs in response to a second control signal.

Abstract: An XOR logic circuit includes a first transfer unit configured to transfer a logic high level data to an output terminal in response to data applied to first and second input terminals; a multiplexing unit configured to output a power voltage or a ground voltage in response to the data applied to the first and second input terminals; and a second transfer unit configured to transfer a logic low level data to the output terminal in response to an output signal of the multiplexing unit and the data applied to the first and second input terminals.

Abstract: An XOR logic circuit includes a first transfer unit configured to transfer a logic high level data to an output terminal in response to data applied to first and second input terminals; a multiplexing unit configured to output a power voltage or a ground voltage in response to the data applied to the first and second input terminals; and a second transfer unit configured to transfer a logic low level data to the output terminal in response to an output signal of the multiplexing unit and the data applied to the first and second input terminals.

Abstract: An XOR logic circuit includes a first transfer unit configured to transfer a logic high level data to an output terminal in response to data applied to first and second input terminals; a multiplexing unit configured to output a power voltage or a ground voltage in response to the data applied to the first and second input terminals; and a second transfer unit configured to transfer a logic low level data to the output terminal in response to an output signal of the multiplexing unit and the data applied to the first and second input terminals.